Silicon-on-insulator devices having contact layer

Patent metadata

Field	Value
Publication number	US-2016336344-A1
Application number	US-201615151867-A
Country	US
Kind code	A1
Filing date	May 11, 2016
Priority date	May 12, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

Silicon-on-insulator (SOI) devices having contact layer. In some embodiments, a radio-frequency (RF) device can include a field-effect transistor (FET) implemented over a substrate layer, and an insulator layer implemented between the FET and the substrate layer. The RF device can further include a contact layer implemented between the insulator layer and the substrate layer to allow adjustment of RF performance of the FET. In some embodiments, such an RF device can be implemented as an RF switch in various products such as a die, a packaged module, and a wireless device.

First claim

1 . A radio-frequency (RF) device comprising:
a field-effect transistor (FET) implemented over a substrate layer an insulator layer implemented between the FET and the substrate layer; and a contact layer implemented between the insulator layer and the substrate layer to allow adjustment of RF performance of the FET.

2 - 15 . (canceled)

16 . The RF device of claim 1 wherein the substrate layer is a part of a silicon-on-insulator (SOI) substrate.

17 . The RF device of claim 16 wherein the substrate layer is a silicon handle layer.

18 - 21 . (canceled)

22 . The RF device of claim 1 further comprising one or more conductive features implemented through the insulator layer and configured to provide an electrical connection to the contact layer.

23 - 48 . (canceled)

49 . The RF device of claim 16 wherein the SOI substrate is configured such that the contact layer is in direct engagement with the insulator layer.

50 . The RF device of claim 16 wherein the SOI substrate includes an interface layer implemented between the substrate layer and an insulator layer.

51 . The RF device of claim 50 wherein the interface layer includes a trap-rich layer.

52 . The RF device of claim 16 wherein the SOI substrate is configured such that substrate layer includes a plurality of doped regions at or near a surface under the insulator layer.

53 . The RF device of claim 52 wherein the doped regions include amorphous and high resistivity properties.

54 . The RF device of claim 52 wherein the doped regions include a crystalline property.

55 . The RF device of claim 1 wherein the contact layer is in direct contact with the substrate layer.

56 . The RF device of claim 55 wherein the contact layer is configured to provide a bias signal to the substrate.

57 . The RF device of claim 1 wherein the contact layer is implemented relative to the FET to provide a back-gate functionality for the FET.

58 . The RF device of claim 57 wherein the contact layer is separated from the FET by a selected distance to provide the back-gate functionality for the FET.

59 . The RF device of claim 58 wherein the selected distance between the FET and the contact layer is achieved by a selected thickness of the insulator layer.

60 . The RF device of claim 1 wherein the contact layer is configured to assist in depletion of or increase in charge in an active channel of the FET.

61 . The RF device of claim 1 wherein the contact layer is implemented to include an area that is generally below the FET.

62 - 67 . (canceled)

68 . A method for fabricating a radio-frequency (RF) device, the method comprising:
forming or providing an assembly that includes a field-effect transistor (FET) over a first side of an insulator layer; and forming a contact layer on a second side of the insulator layer to allow adjustment of RF performance of the FET.

69 . The method of claim 68 further comprising attaching a handle layer to the second side of the insulator layer such that the contact layer is between the insulator layer and the handle layer.

70 - 78 . (canceled)

79 . A method for fabricating a silicon-on-insulator (SOI) device, the method comprising:
forming or providing an SOI wafer having an insulator layer between a front side and a back side; forming a conductive feature through the insulator layer; mounting a carrier on the front side of the SOI wafer; removing some or all of an original handle layer from the back side of the SOI wafer to yield an exposed surface that includes an exposed portion of the conductive feature; forming a contact layer on the exposed surface and in electrical contact with the exposed portion of the conductive feature; and mounting a replacement handle layer over the contact layer.

80 - 101 . (canceled)

Assignees

• Skyworks Solutions Inc

Inventors

• Mason Jerod F
• Whitefield David Scott
• Bartle Dylan Charles

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/656

  Fan-in layouts · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title