Neuromorphic event-driven neural computing architecture in a scalable neural network

Patent metadata

Field	Value
Publication number	US-2015262055-A1
Application number	US-201213585010-A
Country	US
Kind code	A1
Filing date	Aug 14, 2012
Priority date	Sep 16, 2011
Publication date	Sep 17, 2015
Grant date	—

Abstract

An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.

First claim

What is claimed is:

1 . A method for event delivery in a neural network including multiple core circuits, each core circuit comprising an electronic synapse array comprising multiple digital synapses interconnecting a plurality of digital electronic neurons such that each synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron, the method comprising:
in each core circuit, integrating input spikes in an integrate and fire digital neuron, and in response to the integrated inputs exceeding a threshold, sending a spike event to digital synapses interconnecting the neuron to other neurons via the synapse array; and receiving a spike event and scheduling delivery of the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.

2 . The method of claim 1 , wherein scheduling includes delivering the spike event to a selected axon in the synapse array after a delay period.

3 . The method of claim 2 , wherein the delay period is based on a timestamp indicating generation of the spike event and a predetermined delay for event delivery.

4 . The method of claim 1 , wherein scheduling includes selectively imposing a delay on delivery of the received spike events for deterministic event delivery.

5 . The method of claim 1 , wherein scheduling includes delivering events with the same propagation period from event generation.

6 . The method of claim 1 , further comprising:
routing events from a spiking neuron to a destination axon in the synapse array utilizing an intra-circuit event router for one or more core circuits.

7 . The method of claim 6 , wherein an event routing system interconnects the core circuits.

8 . The method of claim 7 , further comprising:
routing events between core circuits using a plurality of inter-circuit event routers.

Assignees

• Akopyan Filipp
• Arthur John V
• Manohar Rajit
• Merolla Paul A
• Modha Dharmendra S
• Molnar Alyosha
• Risk Iii William P
• Univ Cornell
• IBM

Inventors

• Akopyan Filipp
• Arthur John V
• Manohar Rajit
• Merolla Paul A
• Modha Dharmendra S
• Molnar Alyosha
• Risk Iii William P

Classifications

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/06 Primary

  Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/082

  modifying the architecture, e.g. adding, deleting or silencing nodes or connections · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title