Low power read method and a memory device capable thereof

Patent metadata

Field	Value
Publication number	US-12243593-B2
Application number	US-202217685613-A
Country	US
Kind code	B2
Filing date	Mar 3, 2022
Priority date	Mar 3, 2022
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.

First claim

What is claimed is:

1. A memory device, comprising:
a chip including circuitry and a plurality of memory blocks containing an array of memory cells and a plurality of bit lines, the circuitry overlying or underlying the array of memory cells;
the bit lines of the memory blocks being divided into first and second portions that are electrically connected with one another via at least one transistor so that at least one of the first and second portions of each bit line can be charged independently of the other portion of the same bit line; and
a controller configured to
receive a command to sense data from the chip,
determine whether the data can be sensed from the chip by charging only the first portion,
in response to a determination that the data can be sensed by charging only the first portion, put the at least one transistor in an off condition so only the first portion of at least some of the bit lines is charged during a sensing operation, and
in response to a determination that the data cannot be sensed by charging only the first portion, put the at least one transistor in an on condition so that both the first and second portions of each bit line are charged,
wherein the first portions are located on one side of the at least one transistor and the second portions are located on an opposite side of the at least one transistor, and
wherein (i) the circuitry includes a plurality of sense amplifiers that are in electrical communication with the bit lines, (ii) some of the sense amplifiers are electrically connected with the first portions of one or more of the plurality of bit lines, and (iii) others of the sense amplifiers are electrically connected with the second portions of one or more of the plurality of bit lines.

2. The memory device as set forth in claim 1 wherein each of the first and second portions of each bit line are coupled to the at least one transistor by a corresponding bit line hook up.

3. The memory device as set forth in claim 1 wherein the circuitry is located vertically below the plurality of memory blocks.

4. A method of operating a memory device, the method comprising the steps of:
preparing a chip including circuitry and a plurality of memory blocks containing an array of memory cells and a plurality of bit lines, the circuitry overlying or underlying the array of memory cells, and the bit lines of the memory blocks being divided into first and second portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line;
receiving a command to sense data contained in a memory block of the plurality of memory blocks;
determining whether the data can be sensed from the memory block by charging only the first portion;
in response to a determination that the data in the memory block can be sensed by charging only the first portion, putting the at least one transistor in an off condition and charging only the first portion of at least some of the bit lines; and
in response to a determination that the data in the memory block cannot be sensed by charging only the first portion, putting the at least one transistor in an on condition and charging both the first and second portions of each bit line,
wherein the first portions are located on one side of the at least one transistor and the second portions are located on an opposite side of the at least one transistor, and
wherein (i) the circuitry includes a plurality of sense amplifiers that are in electrical communication with the bit lines, (ii) some of the sense amplifiers are electrically connected with the first portions of one or more of the plurality of bit lines, and (iii) others of the sense amplifiers are electrically connected with the second portions of one or more of the plurality of bit lines.

5. The method as set forth in claim 4 wherein the circuitry is located vertically below the plurality of memory blocks.

6. The method as set forth in claim 4 wherein each of the first and second portions of each bit line are coupled to the at least one transistor by a corresponding bit line hook up.

Assignees

• Sandisk Technologies Llc
• Sandisk Technologies Inc

Inventors

• Yang Xiang
• Dutta Deepanshu
• Kwon Ohwon
• Kai James
• Mizutani Yuki

Classifications

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title