Display substrate, display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-12238999-B2
Application number	US-202117629360-A
Country	US
Kind code	B2
Filing date	Feb 7, 2021
Priority date	Feb 7, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A display substrate, a display panel and a display apparatus are provided. The display substrate includes a first display region and a second display region, and a light transmittance of the first display region is greater than a light transmittance of the second display region. A plurality of sub-pixels located in the first display region includes a plurality of sub-pixel groups, each sub-pixel group includes a first sub-pixel and a second sub-pixel, the first pixel driving circuit includes a first sub-pixel driving circuit and a second sub-pixel driving circuit. The first sub-pixel driving circuit includes at least a first reset transistor, the second sub-pixel driving circuit includes at least a second reset transistor, and the first reset transistor of the first sub-pixel driving circuit and the second reset transistor of the second sub-pixel driving circuit are at least partially shared with each other.

First claim

What is claimed is:

1. A display substrate, comprising a first display region and a second display region, a light transmittance of the first display region being greater than a light transmittance of the second display region, wherein the display substrate comprises:
a base substrate;
a plurality of sub-pixels arranged on the base substrate and located in the first display region, the sub-pixels located in the first display region comprising a first pixel driving circuit and a first light-emitting device, the first pixel driving circuit being electrically connected to the first light-emitting device and configured to drive the first light-emitting device to emit light; and
a plurality of sub-pixels arranged on the base substrate and located in the second display region, the sub-pixels located in the second display region comprising a second pixel driving circuit and a second light-emitting device, the second pixel driving circuit being electrically connected to the second light-emitting device and configured to drive the second light-emitting device to emit light,
wherein the plurality of sub-pixels located in the first display region comprise a plurality of sub-pixel groups, each of the plurality of sub-pixel groups comprises a first sub-pixel and a second sub-pixel, the first pixel driving circuit comprises a first sub-pixel driving circuit and a second sub-pixel driving circuit, the first sub-pixel driving circuit is configured to drive the first light-emitting device of the first sub-pixel to emit light, and the second sub-pixel driving circuit is configured to drive the first light-emitting device of the second sub-pixel to emit light, the first sub-pixel driving circuit comprises at least a first reset transistor, the second sub-pixel driving circuit comprises at least a second reset transistor, and the first reset transistor of the first sub-pixel driving circuit and the second reset transistor of the second sub-pixel driving circuit are at least partially shared with each other.

2. The display substrate according to claim 1 , wherein an orthographic projection of each of the first reset transistor of the first sub-pixel driving circuit and the second reset transistor of the second sub-pixel driving circuit on the base substrate falls within an orthographic projection of an occupied region of the first sub-pixel driving circuit on the base substrate.

3. The display substrate according to claim 1 , wherein the first reset transistor comprises a common transistor and a first sub-transistor, and the second reset transistor comprises the common transistor and a second sub-transistor, and each of the common transistor, the first sub-transistor and the second sub-transistor comprises a gate, a source and a drain, and the gate of each of the common transistor, the first sub-transistor and the second sub-transistor is configured to receive a reset control signal, one of the source or the drain of the common transistor is configured to receive an initialization voltage signal, and the other of the source or the drain of the common transistor is electrically connected to the first sub-transistor and the second sub-transistor, respectively.

4. The display substrate according to claim 3 , wherein the display substrate further comprises a semiconductor layer arranged on the base substrate and a first conductive layer located on a side of the semiconductor layer away from the base substrate, and the display substrate further comprises a reset signal line arranged on the base substrate, the reset signal line is configured to transmit the reset control signal, and the reset signal line is located in the first conductive layer; and
the reset signal line comprises a first part, a second part and a third part located in the first display region, and the semiconductor layer comprises a common channel portion, a first channel portion and a second channel portion located in the first display region, orthographic projections of the first part, the second part and the third part on the base substrate are respectively coincide with orthographic projections of the common channel portion, the first channel portion and the second channel portion on the base substrate, the gate of the common transistor comprises the first part, the gate of the first sub-transistor comprises the second part, and the gate of the second sub-transistor comprises the third part.

5. The display substrate according to claim 4 , wherein the common transistor comprises a common source portion and a common drain portion located in the semiconductor layer, the first sub-transistor comprises a first sub-source portion and a first sub-drain portion located in the semiconductor layer, and the second sub-transistor comprises a second sub-source portion and a second sub-drain portion located in the semiconductor layer;
wherein the common source portion and the common drain portion are respectively located on both sides of the common channel portion, the first sub-source portion and the first sub-drain portion are respectively located on both sides of the first channel portion, and the second sub-source portion and the second sub-drain portion are respectively located on both sides of the second channel portion;
wherein the display substrate further comprises an initialization voltage line arranged on the base substrate and a first connection portion arranged on the base substrate;
wherein one of the common source portion and the common drain portion is electrically connected to the initialization voltage line through a first via hole, and the other of the common source portion and the common drain portion extends continuously with one of the first sub-source portion and the first sub-drain portion;
wherein the other of the first sub-source portion and the first sub-drain portion is electrically connected to one end of the first connection portion through a second via hole; and
wherein the first sub-pixel driving circuit further comprises a first driving transistor comprising a gate, and the other end of the first connection portion is electrically connected to the gate of the first driving transistor through a third via hole.

6. The display substrate according to claim 5 , wherein the display substrate further comprises a first transparent conductive connection portion arranged on the base substrate;
the other of the common source portion and the common drain portion further extends continuously with one of the second sub-source portion and the second sub-drain portion; and
the other of the second sub-source portion and the second sub-drain portion is electrically connected to one end of the first transparent conductive connection portion through the third via hole.

7. The display substrate according to claim 6 , wherein the second sub-pixel driving circuit further comprises a second driving transistor comprising a gate, and the other end of the first transparent conductive connection portion is electrically connected to the gate of the second driving transistor through a fourth via hole.

8. The display substrate according to claim 6 , wherein the initialization voltage line is located in a second conductive layer, the first connection portion is located in a third conductive layer, the second conductive layer is located on a side of the first conductive layer away from the base substrate, and the third conductive layer is located on a side of the second conductive layer away from the base substrate; and
wherein the first transparent conductive connection portion is located in a first transparent conductive layer, and the first transparent conductive layer is located on a side of the third conductive layer away from the base substrate.

9. The display substrate according to claim 6 , wherein t

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Chengdu Boe Optoelectronis Tech Co Ltd

Inventors

• Liu Ke
• Shi Ling
• Chen Yipeng
• Liu Lang
• Zhang Zhenhua
• Tian Xuewei

Classifications

• H10K59/12

  Active-matrix OLED [AMOLED] displays · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/353 Primary

  characterised by the geometrical arrangement of the RGB subpixels · CPC title

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title