Integrated circuit device

Patent metadata

Field	Value
Publication number	US-12237383-B2
Application number	US-202117404078-A
Country	US
Kind code	B2
Filing date	Aug 17, 2021
Priority date	Jan 27, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a substrate, a gate line extending in a second lateral direction on the fin-type active region, an insulating spacer covering a sidewall of the gate line, a source/drain region at a position adjacent to the gate line, a metal silicide film covering a top surface of the source/drain region, and a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction. The source/drain contact includes a bottom contact segment being in contact with a top surface of the metal silicide film and an upper contact segment integrally connected to the bottom contact segment. A width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a fin-type active region extending in a first lateral direction on a substrate;
a gate line extending in a second lateral direction, the gate line being on the fin-type active region, the second lateral direction intersecting with the first lateral direction;
an insulating spacer covering a sidewall of the gate line;
a source/drain region connected to the fin-type active region adjacent to the gate line and spaced apart from the insulating spacer, the source/drain region having a dopant profile different from a dopant profile of the fin-type active region;
a metal silicide film covering a top surface of the source/drain region; and
a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction, the source/drain contact being connected to the source/drain region through the metal silicide film,
the source/drain contact including a bottom contact segment and an upper contact segment, the bottom contact segment having a contact surface in contact with a top surface of the metal silicide film, the upper contact segment being apart from the metal silicide film with the bottom contact segment therebetween in a vertical direction, the upper contact segment being integrally connected to the bottom contact segment, wherein a width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction,
the metal silicide film contacting the insulating spacer and a region of the fin-type active region having the dopant profile of the fin-type active region.

2. The integrated circuit device of claim 1 , wherein the bottom contact segment of the source/drain contact includes a portion protruding from a lower end of the upper contact segment toward the gate line.

3. The integrated circuit device of claim 1 , wherein, in the first lateral direction, a width of the contact surface of the bottom contact segment is equal to a width of the metal silicide film and greater than a minimum width of the upper contact segment.

4. The integrated circuit device of claim 1 , wherein, in the first lateral direction, a width of the contact surface of the bottom contact segment is less than a width of the metal silicide film and greater than a minimum width of the upper contact segment.

5. The integrated circuit device of claim 1 , wherein each of the bottom contact segment of the source/drain contact and the metal silicide film includes a portion in contact with the insulating spacer.

6. The integrated circuit device of claim 1 , the integrated circuit device further comprising an insulating liner between the insulating spacer and the upper contact segment of the source/drain contact,
wherein the bottom contact segment of the source/drain contact includes a portion between the metal silicide film and the insulating liner in the vertical direction.

7. The integrated circuit device of claim 1 , the integrated circuit device further comprising an insulating liner between the insulating spacer and the upper contact segment of the source/drain contact,
wherein a bottom surface of the insulating liner, which faces the substrate, includes a horizontal plane extending in the first lateral direction at a position apart from the metal silicide film in the vertical direction.

8. The integrated circuit device of claim 1 , the integrated circuit device further comprising an insulating liner between the insulating spacer and the upper contact segment of the source/drain contact,
wherein
a bottom surface of the insulating liner, which faces the substrate, includes an inclined bottom surface extending in an inclined direction that intersects with the first lateral direction, and
the bottom contact segment includes an inclined outer wall in contact with the inclined bottom surface.

9. The integrated circuit device of claim 1 , the integrated circuit device further comprising an insulating liner between the insulating spacer and the upper contact segment of the source/drain contact,
wherein a bottom surface of the insulating liner, which faces the substrate, includes an inclined bottom surface extending in an inclined direction that intersects with the first lateral direction at a position apart from the metal silicide film in the vertical direction.

10. The integrated circuit device of claim 1 , the integrated circuit device further comprising an insulating liner between the insulating spacer and the upper contact segment of the source/drain contact,
wherein a bottom surface of the insulating liner, which faces the substrate, includes an inclined bottom surface in contact with the metal silicide film.

11. The integrated circuit device of claim 1 , a maximum width of the metal silicide film is greater than or equal to a maximum width of the source/drain contact in the first lateral direction.

12. An integrated circuit device comprising:
a fin-type active region extending in a first lateral direction on a substrate;
a recess region defined by the fin-type active region;
a pair of gate lines apart from each other with the recess region therebetween, the pair of gate lines extending in a second lateral direction on the fin-type active region, the second lateral direction intersecting with the first lateral direction;
a pair of insulating spacers covering sidewalls of each of the pair of gate lines;
a source/drain region in the recess region, connected to the fin-type active region adjacent to the gate line and spaced apart from the pair of insulating spacers, the source/drain region having a dopant profile different from a dopant profile of the fin-type active region;
a metal silicide film covering a top surface of the source/drain region; and
a source/drain contact between the pair of gate lines, the source/drain contact being connected to the source/drain region through the metal silicide film, the source/drain contact including a bottom contact segment and an upper contact segment, the bottom contact segment having a contact surface in contact with a top surface of the metal silicide film, the upper contact segment being apart from the metal silicide film with the bottom contact segment therebetween in a vertical direction, the upper contact segment being integrally connected to the bottom contact segment, a width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction,
the metal silicide film contacting the pair of insulating spacers and a region of the fin-type active region having the dopant profile of the fin-type active region.

13. The integrated circuit device of claim 12 , wherein the bottom contact segment of the source/drain contact includes portions protruding in opposite directions from a lower end of the upper contact segment toward the pair of gate lines in the first lateral direction.

14. The integrated circuit device of claim 12 , wherein the metal silicide film is in contact with the pair of insulating spacers.

15. The integrated circuit device of claim 12 , the integrated circuit device further comprising an insulating liner between the pair of insulating spacers, the insulating liner covering a sidewall of the upper contact segment of the source/drain contact,
wherein the metal silicide film is in contact with each of the pair of insulating spacers and apart from the insulating liner in the vertical direction, and
the bottom contact segment of the source/drain contact is in contact with each of the pair of insulating spacers.

16. The integ

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dohee
• Kim Gyeom
• Kim Jinbum
• Kim Jaemun
• Lee Seunghun

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title