Semiconductor devices with shaped portions of elevated source/drain regions

Patent metadata

Field	Value
Publication number	US-10043902-B2
Application number	US-201514963731-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	May 24, 2012
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

First claim

What is claimed:

1. A semiconductor device comprising:
a first interlayer insulating film, which comprises an aperture, on a substrate;
a gate in the aperture;
an elevated source/drain on both sides of the gate;
a second interlayer insulating film on the first interlayer insulating film and the gate;
a metal silicide formed in at least part of the elevated source/drain; and
a metal contact passing through the first and second interlayer insulating film and on the metal silicide,
wherein the elevated source/drain comprises a protruding portion which protrudes further than a surface of the substrate and covers both sides of the metal silicide, wherein the metal silicide comprises a reversed cone shape with a rounded apex, a planar upper surface, and a tapered side surface that extends from the rounded apex to the planar upper surface, wherein the rounded apex faces toward the substrate, wherein a recess is formed within the reversed cone shape at the planar upper surface thereof, the recess comprising a recess bottom and a circumferentially extending recess sidewall, wherein a vertical length from the recess bottom to the rounded apex is longer than a horizontal length from the recess sidewall to the side surface of the reversed cone shape, and wherein the horizontal length varies from the recess bottom to the planar upper surface of the reversed cone shape.

2. The semiconductor device of claim 1 , wherein the protruding portion becomes narrower as a distance from the surface of the substrate increases.

3. The semiconductor device of claim 1 , wherein the metal silicide is not formed in at least part of a surface of the elevated source/drain.

4. The semiconductor device of claim 1 , wherein the semiconductor device comprises a p-channel metal oxide semiconductor (PMOS) transistor, wherein the elevated source/drain contains SiGe.

5. The semiconductor device of claim 4 , further comprising:
a barrier layer formed between the metal silicide and the metal contact; and
wherein the metal silicide surrounds part of the barrier layer.

6. The semiconductor device of claim 1 , being an n-channel metal oxide semiconductor (NMOS) transistor, wherein the elevated source/drain contains Si.

7. The semiconductor device of claim 1 , wherein the gate comprises a first metal layer conformally formed along sidewalls and a bottom surface of the aperture and a second metal layer formed on the first metal layer in the aperture to fill the aperture.

8. The semiconductor device of claim 1 wherein an angle defined by a lowest point of the rounded apex and the tapered side surface is between 30 degrees and 70 degrees.

9. The semiconductor device of claim 1 , wherein the metal silicide comprises at least one of nickel (Ni) and platinum (Pt).

Assignees

• Shin Chung Hwan
• Kang Sang Bom
• Kim Dae Yong
• Kim Jeong Ik
• Kim Chul Sung
• Ryu Je Hyung
• Lee Sang Woo
• Choi Hyo Seok
• Samsung Electronics Co Ltd

Inventors

• Shin Chung-Hwan
• Kang Sang-Bom
• Kim Dae-Yong
• Kim Jeong-Ik
• Kim Chul-Sung
• Ryu Je-Hyung
• Lee Sang-Woo
• Choi Hyo-Seok

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10D64/0121

  to Group IV semiconductors · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title