Contact resistance optimization via EPI growth engineering

Patent metadata

Field	Value
Publication number	US-9673295-B2
Application number	US-201414287506-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	May 27, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.

First claim

What is claimed is:

1. A method comprising:
forming a semiconductor substrate having a top surface and an opening wherein the opening has a bottom and a sidewall and wherein the top surface has a gate structure on either side of the opening and wherein each gate structure has a spacer which is adjacent and directly contacts the gate structure and wherein the spacer is positioned on the substrate top surface;
forming a first semiconductor layer in the opening such that the first semiconductor layer top surface is non-planar and includes:
a first valley positioned below the top surface of the substrate; and
a first peak laterally adjacent to the valley and positioned above the top surface of the substrate;

forming a second semiconductor layer on top of the first semiconductor layer top surface and in direct contact with the spacer; and
forming a silicide by reacting with a portion of the second semiconductor layer in a remaining portion of the second semiconductor layer to form a silicide-first semiconductor interface which includes a second valley positioned above the first valley, wherein after forming the silicide, both the silicide and the remaining portion of the second semiconductor layer directly contact the first semiconductor layer, and all the silicide is separated from the semiconductor substrate by at least one of the first semiconductor layer and the remaining portion of the second semiconductor layer.

2. The method of claim 1 , wherein the first semiconductor layer comprises a dopant which imparts a stress to a channel region of a transistor.

3. The method of claim 2 , wherein the second semiconductor film comprises a second dopant wherein the second dopant is different from the dopant which imparts the stress to the channel region.

4. The method of claim 1 , wherein the first valley is centered laterally with respect to the opening.

5. The method of claim 1 , wherein the second semiconductor layer has a higher defect density than the first semiconductor layer.

6. The method of claim 5 wherein forming the silicide occurs preferentially in the second semiconductor layer.

7. The method of claim 1 , wherein the first semiconductor layer top surface is “M” shaped.

8. The method of claim 7 wherein forming the first semiconductor layer occurs by using a deposition process and an etching process.

9. The method of claim 8 wherein the deposition process and the etching process are selected from a group consisting of cyclic and simultaneous.

10. The method of claim 1 , further comprising forming a pair of additional spacers on the second semiconductor layer, such that each of the pair of additional spacers contacts the spacer of the gate structure on a respective sidewall of the opening, after forming the second semiconductor layer.

11. The method of claim 10 , wherein the second semiconductor layer and the silicide are positioned vertically between the first semiconductor layer and the pair of additional spacers.

12. A method comprising:
forming a semiconductor substrate having a top surface and an opening wherein the opening has a bottom and a sidewall and wherein the top surface has a gate structure on either side of the opening and wherein each gate structure has a spacer which is adjacent and directly contacts the gate structure and wherein the spacer is in contact with the substrate top surface;
forming a first semiconductor layer in the opening such that the first semiconductor layer top surface is non-planar and includes: a first laterally-centered valley positioned below the top surface of the substrate, and a pair of first peaks each laterally adjacent to the valley and positioned above the top surface of the substrate;
growing a second semiconductor layer directly on top of the first semiconductor layer top surface and in direct contact with the spacer thereby forming a first semiconductor layer-second semiconductor layer interface which is non-planar and includes a second valley positioned above the first valley and a pair of second peaks each positioned above one of the pair of first peaks; and
forming a silicide by reacting with a portion of the second semiconductor layer in a remaining portion of the second semiconductor layer to form a silicide-first semiconductor interface from the first semiconductor layer-second semiconductor layer interface which includes the second valley and the pair of second peaks, wherein after forming the silicide, both the silicide and the remaining portion of the second semiconductor layer directly contact the first semiconductor layer, and all the silicide is separated from the semiconductor substrate by at least one of the first semiconductor layer and the remaining portion of the second semiconductor layer.

13. The method of claim 12 , wherein the first semiconductor layer includes a stress-inducing dopant for a channel region of a transistor, and wherein the forming of the silicide-first semiconductor interface with the second valley causes the stress-inducing dopant to migrate from the first semiconductor layer to a channel region of a transistor.

14. The method of claim 12 , wherein each of the first valley and the second valley are one of U-shaped, V-shaped, or M-shaped.

15. The method of claim 12 , wherein a height of the pair of first peaks above the top surface of the substrate prevents encroachment of the formed silicide into the semiconductor substrate.

16. The method of claim 12 , further comprising forming a pair of additional spacers on the second semiconductor layer, such that each of the pair of additional spacers contacts the spacer of the gate structure on a respective sidewall of the opening, after forming the second semiconductor layer.

17. A method comprising:
forming a semiconductor substrate having a top surface and an opening wherein the opening has a bottom and a sidewall and wherein the top surface has a gate structure on either side of the opening and wherein each gate structure has a spacer which is adjacent and directly contacts the gate structure and wherein the spacer is positioned on the substrate top surface;
forming a first semiconductor layer in the opening such that the first semiconductor layer top surface is non-planar and includes: a first laterally-centered valley positioned below the top surface of the substrate, and a first peak laterally adjacent to the first laterally-centered valley and positioned above the top surface of the substrate, wherein a distance between a top surface of the first peak and a bottom surface of the first laterally-centered valley is at most approximately thirty nanometers;
forming a second semiconductor layer on top of the first semiconductor layer top surface and in direct contact with the spacer, wherein a top surface of the second semiconductor layer includes a second laterally-centered valley and a second peak;
forming a pair of additional spacers on the second semiconductor layer, such that each of the pair of additional spacers contacts the spacer of the gate structure on a respective sidewall of the opening, after forming the second semiconductor layer; and
forming a silicide by reacting with a portion of the second semiconductor layer in a remaining portion of the second semiconductor layer to form a silicide-first semiconductor interface which includes the second laterally-centered valley and the second peak, wherein after forming the silicide, both the silicide and the remaining portion of the second semiconductor layer directly contact the first semiconductor layer, and all the silicide is separated from the semiconductor substrate by at least one

Assignees

• Globalfoundries Inc

Inventors

• Levesque Annie
• Ontalus Viorel C
• Stoker Matthew W

Classifications

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H01L29/165

  Electricity · mapped topic

• H01L29/66628

  Electricity · mapped topic

• H01L21/28518

  Electricity · mapped topic