Integrated circuit package having wirebonded multi-die stack

Patent metadata

Field	Value
Publication number	US-12237305-B2
Application number	US-202217958298-A
Country	US
Kind code	B2
Filing date	Sep 30, 2022
Priority date	Sep 26, 2014
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first die having an active side and a backside opposite the active side, the active side having a plurality of die level interconnects thereon;
a redistribution layer, the redistribution layer coupled to the active side of the first die, and the redistribution layer coupled to a plurality of package level interconnects;
a first via bar laterally adjacent to and spaced apart from a first edge of the first die, the first via bar coupled to the redistribution layer, and the first via bar extending above the backside of the first die;
a second via bar laterally adjacent to and spaced apart from a second edge of the first die opposite the first edge of the first die, the second via bar coupled to the redistribution layer, and the second via bar extending above the backside of the first die;
a first encapsulation layer laterally surrounding and in contact with the first die;
an electrically insulative material in direct physical contact with the first encapsulation layer, and the electrically insulative material having an uppermost surface above a level of the backside of the first die, wherein the first via bar and the second via bar are within and in contact with the electrically insulative material;
a second die above the first die, the second die having an active side and a backside opposite the active side, the active side of the second die having a plurality of die level interconnects thereon, the backside of the second die facing the backside of the first die;
a third die above the second die, the third die having an active side and a backside opposite the active side, the active side of the third die having a plurality of die level interconnects thereon, the backside of the third die facing the active side of the second die;
a first wire bond coupling one of the plurality of die level interconnects of the second die to the first via bar;
a second wire bond coupling one of the plurality of die level interconnects of the third die to the second via bar; and
a second encapsulation layer laterally adjacent the second die, the third die, the first wire bond, and the second wire bond, wherein the second encapsulation layer is further over the active side of the third die.

2. The semiconductor package of claim 1 , further comprising:
a spacer between the backside of the third die and the active side of the second die.

3. The semiconductor package of claim 2 , wherein the second encapsulation layer is laterally adjacent the spacer.

4. The semiconductor package of claim 1 , further comprising:
a first conductive pad between the first wire bond and the first via bar; and
a second conductive pad between the second wire bond and the second via bar.

5. The semiconductor package of claim 1 , wherein the plurality of package level interconnects comprises a plurality of solder balls below the first die and outside of a periphery of the first die.

6. The semiconductor package of claim 1 , wherein the plurality of package level interconnects comprises a plurality of solder balls below the first die and within a periphery of the first die.

7. The semiconductor package of claim 1 , wherein the plurality of package level interconnects comprises a first plurality of solder balls below the first die and within a periphery of the first die, and a second plurality of solder balls below the first die and outside of the periphery of the first die.

8. The semiconductor package of claim 1 , further comprising:
a second redistribution layer between the redistribution layer and the plurality of package level interconnects.

9. The semiconductor package of claim 1 , wherein the second die and the third die are vertically aligned with one another.

10. The semiconductor package of claim 1 , wherein the first encapsulation layer has an uppermost surface above the backside of the first die.

11. The semiconductor package of claim 1 , further comprising:
a fourth die having an active side coupled to a die side of the redistribution layer.

12. An integrated circuit (IC) assembly comprising:
a semiconductor package, comprising:
a first integrated circuit having an active side and a backside opposite the active side, the active side having a plurality of die level interconnects thereon;
a redistribution layer, the redistribution layer coupled to the active side of the first integrated circuit, and the redistribution layer coupled to a plurality of package level interconnects;
a first via bar laterally adjacent to and distanced apart from a first edge of the first integrated circuit, the first via bar coupled to the redistribution layer, and the first via bar extending above the backside of the first integrated circuit;
a second via bar laterally adjacent to and distanced apart from a second edge of the first integrated circuit opposite the first edge of the first integrated circuit, the second via bar coupled to the redistribution layer, and the second via bar extending above the backside of the first integrated circuit;
a first encapsulation layer laterally surrounding and in contact with the first integrated circuit;
an electrically insulative material in direct physical contact with the first encapsulation layer, and the electrically insulative material having an uppermost surface above a level of the backside of the first integrated circuit, wherein the first via bar and the second via bar are within and in contact with the electrically insulative material;
a second integrated circuit above the first integrated circuit, the second integrated circuit having an active side and a backside opposite the active side, the active side of the second integrated circuit having a plurality of integrated circuit level interconnects thereon, the backside of the second integrated circuit facing the backside of the first integrated circuit;
a third integrated circuit above the second integrated circuit, the third integrated circuit having an active side and a backside opposite the active side, the active side of the third integrated circuit having a plurality of integrated circuit level interconnects thereon, the backside of the third integrated circuit facing the active side of the second integrated circuit;
a first wire bond electrically connecting one of the plurality of integrated circuit level interconnects of the second integrated circuit to the first via bar;
a second wire bond electrically connecting one of the plurality of integrated circuit level interconnects of the third integrated circuit to the second via bar; and
a second encapsulation layer laterally adjacent the second integrated circuit, the third integrated circuit, the first wire bond, and the second wire bond, wherein the second encapsulation layer is further over the active side of the third integrated circuit; and
a circuit board having a plurality of electrical routing features disposed therein and a plurality of pads disposed thereon, wherein the plurality of pads are electrically coupled with the plurality of package level interconnects.

13. The IC assembly of claim 12 , wherein the semiconductor package includes a processor.

14. The IC assembly of claim 12 , wherein the semiconductor package includes a memory.

15. The IC assembly of claim 12 , further comprising one or more components coupled to the circuit board, the one or more components selected from the group consisting of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a

Assignees

• Intel Corp

Inventors

• Meyer Thorsten
• Jaervinen Pauli
• Patten Richard

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/231

  the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure · CPC title