Integrated circuit package having wirebonded multi-die stack
US-2025167180-A1 · May 22, 2025 · US
Jaervinen Pauli is listed as an inventor on 11 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Jaervinen Pauli |
| Total patents | 11 |
| First publication | Aug 18, 2016 |
| Latest publication | May 22, 2025 |
Publications ranked by popularity score, then publication date.
US-2025167180-A1 · May 22, 2025 · US
US-12237305-B2 · Feb 25, 2025 · US
US-2023023328-A1 · Jan 26, 2023 · US
US-10319688-B2 · Jun 11, 2019 · US
US-10249598-B2 · Apr 2, 2019 · US
US-2018315737-A1 · Nov 1, 2018 · US
US-2018197840-A1 · Jul 12, 2018 · US
US-9972601-B2 · May 15, 2018 · US
US-9819327-B2 · Nov 14, 2017 · US
US-2016276311-A1 · Sep 22, 2016 · US
Latest publications not already listed above.
US-2016240492-A1 · Aug 18, 2016 · US
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 10 |
| Maruthamuthu Saravana | 1 |
| Meyer Thorsten | 1 |
| Herrero Pablo | 1 |
| Wolter Andreas | 1 |
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W74/00 | 10 |
| H10W70/60 | 10 |
| H10W90/00 | 10 |
| H10W70/09 | 10 |
| H10W90/724 | 10 |