Electronic devices comprising multilevel bitlines, and related methods and systems

Patent metadata

Field	Value
Publication number	US-12237259-B2
Application number	US-202117443531-A
Country	US
Kind code	B2
Filing date	Jul 27, 2021
Priority date	Jul 27, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

First claim

What is claimed is:

1. An electronic device comprising:
multilevel bitlines comprising first bitlines and second bitlines, the first bitlines and the second bitlines positioned at different levels;
level 1 contacts electrically connected to the first bitlines; and
level 2 contacts electrically connected to the second bitlines;
a liner between the first bitlines and the level 2 contacts; and
each bitline of the first bitlines electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines electrically connected to a single pillar contact adjacent to the level 2 contacts.

2. The electronic device of claim 1 , wherein the bitlines of the first bitlines are equally spaced from one another.

3. The electronic device of claim 1 , wherein the bitlines of the second bitlines are equally spaced from one another.

4. The electronic device of claim 1 , wherein the second bitlines exhibit a greater width than a width of the level 2 contacts.

5. The electronic device of claim 1 , wherein the liner is coextensive with a height of the level 2 contacts.

6. The electronic device of claim 1 , wherein the liner is laterally adjacent to the first bitlines and the level 2 contacts.

7. The electronic device of claim 1 , wherein the liner is between the first bitlines and the level 2 contacts only proximal to the first bitlines.

8. The electronic device of claim 7 , wherein a height of the liner is less than a height of the first bitlines.

9. The electronic device of claim 1 , wherein adjacent second bitlines are separated by a dielectric material.

10. The electronic device of claim 1 , wherein adjacent second bitlines are separated by air gaps.

11. The electronic device of claim 10 , wherein adjacent level 2 contacts are separated by the air gaps.

12. The electronic device of claim 1 , wherein a spacing between adjacent first bitlines is relatively smaller than a diameter of the level 2 contacts.

13. The electronic device of claim 1 , wherein the first bitlines and the second bitlines at least partially overlap in a vertical direction.

14. A system, comprising:
a processor operably coupled to an input device and an output device; and
one or more electronic devices operably coupled to the processor, the one or more electronic devices comprising:
multilevel bitlines comprising first bitlines and second bitlines, the first bitlines and the second bitlines positioned at different levels and the first bitlines and the second bitlines electrically connected to memory cells, the first bitlines and the second bitlines being electrically connected to pillar contacts;
level 1 contacts electrically connected to the first bitlines; and
level 2 contacts electrically connected to the second bitlines and separated from laterally adjacent first bitlines by a liner.

15. The system of claim 14 , wherein the liner is coextensive with the level 2 contacts.

16. The system of claim 14 , wherein a height of the liner is less than a height of the first bitlines.

17. The system of claim 14 , wherein a height of the liner is greater than a height of the first bitlines and less than a height of the level 2 contacts.

18. The system of claim 14 , wherein air gaps separate laterally adjacent second bitlines from one another.

19. The system of claim 14 , wherein a horizontal spacing between the first bitlines is relatively narrower than a diameter of the level 2 contacts between the first bitlines.

20. A method of forming an electronic device, comprising:
forming a first level comprising first bitlines and level 1 contacts in a first dielectric material, the level 1 contacts electrically connected to the first bitlines;
forming a second dielectric material adjacent to the first level;
forming openings through the second dielectric material and into the first dielectric material;
forming a liner in the openings;
forming a conductive material in the openings to form level 2 contacts adjacent to the liner, the liner between the first bitlines and the level 2 contacts; and
forming second bitlines in electrical contact with the level 2 contacts, the first bitlines and the second bitlines positioned at different levels and each bitline of the first bitlines electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines electrically connected to a single pillar contact adjacent to the level 2 contact.

21. The method of claim 20 , wherein forming openings through the second dielectric material and into the first dielectric material comprises removing a portion of the first bitlines.

22. The method of claim 20 , wherein forming second bitlines in electrical contact with the level 2 contacts comprises forming the second bitlines exhibiting a greater width than a diameter of the level 2 contacts.

23. The method of claim 20 , wherein forming a conductive material in the openings to form level 2 contacts adjacent to the liner comprises forming the level 2 contacts coextensive with the liner.

24. The method of claim 20 , further comprising removing the second dielectric material to form air gaps adjacent to the second bitlines.

25. The method of claim 24 , wherein removing the second dielectric material comprises extending the air gaps from an upper surface of the second bitlines to below the first bitlines.

26. The method of claim 25 , wherein removing the second dielectric material comprises forming the air gaps laterally adjacent to the second bitlines and to the liner.

27. The method of claim 24 , further comprising removing a portion of the liner adjacent to the level 2 contacts.

28. The method of claim 27 , wherein removing a portion of the liner comprises extending the air gaps to be laterally adjacent to the first bitlines.

Assignees

• Micron Technology Inc

Inventors

• Fukuzumi Yoshiaki
• Jain Harsh Narendrakumar
• Kaushik Naveen
• Olson Adam L
• Hill Richard J
• Heineck Lars P

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title