Memory device having 2-transistor vertical memory cell

Patent metadata

Field	Value
Publication number	US-12232311-B2
Application number	US-202318388769-A
Country	US
Kind code	B2
Filing date	Nov 10, 2023
Priority date	Dec 26, 2018
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels.

First claim

What is claimed is:

1. An apparatus comprising:
a memory cell including:
a first transistor including a charge storage structure and a first channel region separated from the charge storage structure; and
a second transistor including a second channel region coupled to the charge storage structure, wherein the charge storage structure is between the second channel region and the first channel region;

a conductive region coupled to the first channel region;
a data line coupled to one of the first channel region and the second channel region; and
at least one access line separated from the first channel region and the second channel region.

2. The apparatus of claim 1 , wherein the first channel region and the second channel region include different materials.

3. The apparatus of claim 1 , further comprising an additional data line coupled to the first channel region, wherein the data line is coupled to the second channel region.

4. The apparatus of claim 3 , further comprising a further data line coupled to the first channel region.

5. The apparatus of claim 1 , wherein the data line includes a length in a first direction, and the at least one access line includes a length in a second direction.

6. The apparatus of claim 1 , wherein the at least one access line includes:
a first access line adjacent the first channel region separated from the first channel region by a first dielectric material; and
a second access line adjacent the second channel region and separated from the second channel region by a second dielectric material.

7. The apparatus of claim 2 , wherein the second access line is between the first access line and the data line.

8. The apparatus of claim 2 , wherein the first access line and the second access line are coupled to each other.

9. An apparatus comprising:
a memory cell including:
a first transistor including a charge storage structure and a first channel region, the storage structure including a first side, a second side opposite from the first side, and a third side between the first side and the second side, and a first channel region separated from the charge storage structure, the first channel region including a first portion located on the first side of the charge storage structure, a second portion located on the second side of the charge storage structure, and a third portion located on the third side of the charge storage structure; and
a second transistor including a second channel region coupled to the charge storage structure;

at least one data line associated with the memory cell and coupled to the first channel region; and
at least one access line associated with the memory cell.

10. The apparatus of claim 9 , wherein the at least on data line includes a first data line coupled to the first channel region, and a second data line coupled to the second channel region.

11. The apparatus of claim 10 , wherein the at least on data line includes a third data line coupled to the first channel region.

12. The apparatus of claim 9 , wherein the at least one access line includes:
a first access line adjacent the first channel region separated from the first channel region by a first dielectric material; and
a second access line adjacent the second channel region and separated from the second channel region by a second dielectric material.

13. The apparatus of claim 11 , wherein the second channel region includes a semiconducting oxide material.

14. An apparatus comprising:
a memory cell including:
a first transistor including a charge storage structure including a first side and a second side opposite from the first side, and a first channel region separated from the charge storage structure; and
a second transistor including a second channel region located on the first side of the charge storage structure and coupled to the charge storage structure;

a data line located on the second side of the charge storage structure and separated from the charge storage structure, the data line coupled to the first channel region and including a length in a first direction;
a conductive region coupled to the first channel region; and
at least one access line associated with the memory cell and including length in a second direction.

15. The apparatus of claim 14 , wherein the conductive region is coupled to a ground connection.

16. The apparatus of claim 14 , further comprising an additional data line coupled to the second channel region.

17. The apparatus of claim 14 , wherein the at least one access line includes a portion spanning across part of the first channel region and part of the charge storage structure.

18. The apparatus of claim 17 , wherein the at least one access line includes:
a first access line spanning across part of the first channel region and part of the charge storage structure; and
a second access line adjacent the second channel region and separated from the second channel region by a second dielectric material.

19. The apparatus of claim 18 , wherein the conductive region is between the first access line and the second access line.

20. The apparatus of claim 18 , wherein the second access line is between the data line and the conductive region.

Assignees

• Micron Technology Inc

Inventors

• Pulugurtha Srinivas
• Ramaswamy Durai Vishak Nirmal

Classifications

• H10B12/01

  Manufacture or treatment · CPC title

• G11C11/408

  Address circuits · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title