Recess structure for padless stack via

Patent metadata

Field	Value
Publication number	US-12230552-B2
Application number	US-202117455576-A
Country	US
Kind code	B2
Filing date	Nov 18, 2021
Priority date	Nov 18, 2021
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

Disclosed is a stack via structure in which a plurality of vias are stacked over each other. At least one via is a via that has a recess formed from a top surface thereof. Another via above the via is formed such that a bottom portion of the another via is in the recess of the via. In this way, no capture pad is needed between the via and the another via. Also, contact area between the via and the another via is enhanced.

First claim

What is claimed is:

1. A stack via structure, comprising:
a capture pad;
a first via stacked over and electrically coupled with the capture pad;
a second via stacked over and electrically coupled with the first via;
a cover pad stacked over and electrically coupled with the second via;
a first dielectric layer encapsulating sides of the first via, wherein a top surface of the first via and a top surface of the first dielectric layer are coplanar; and
a second dielectric layer formed on the first dielectric layer and encapsulating sides of the second via,
wherein a top width the first via is wider than a bottom width of the second via,
wherein a recess is formed in the first via to partially extend into the top surface thereof, and
wherein a bottom portion of the second via is within the recess, the bottom portion of the second via extending from a bottom surface thereof up to a height equal to a depth of the recess, the second via being in contact with the first via within the recess.

2. The stack via structure of claim 1 ,
wherein the first via is tapered such that the top width thereof is wider than a bottom width thereof,
wherein the second via is tapered such that a top width thereof is wider than the bottom width thereof, and
wherein the recess is tapered such that a top width thereof is wider than a bottom width thereof.

3. The stack via structure of claim 1 , wherein
a side surface of the bottom portion of the second via is in contact with a side surface of the recess, and
a bottom surface of the bottom portion of the second via is in contact with a bottom surface of the recess.

4. The stack via structure of claim 1 , wherein there is no capture pad between the first via and the second via.

5. The stack via structure of claim 1 , wherein the second via is electrically coupled with another via at a same layer through a pattern line, the second via being in contact with the pattern line.

6. The stack via structure of claim 1 , wherein the cover pad is a pad within a cover layer of a stack layer structure that comprises the stack via structure, the cover layer being an outermost layer of the stack layer structure, and the cover pad being configured to enable a signal connection with an external device.

7. The stack via structure of claim 1 , wherein between the first via and the second via, the capture pad is electrically coupled to the cover pad through the first via and the second via in that order.

8. The stack via structure of claim 1 , wherein the first via is formed from copper (Cu), the second via is formed from copper (Cu), or both.

9. The stack via structure of claim 1 , wherein the depth of the recess ranges between 5% and 15% of a height of the first via.

10. The stack via structure of claim 1 , wherein the stack via structure is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

11. A stack layer structure, comprising:
a capture pad and an inner via formed in an inner dielectric layer, the inner via being stacked over and electrically coupled with the capture pad, wherein a top surface of the inner via and a top surface of the inner dielectric layer are coplanar;
one or more intermediate vias formed in corresponding one or more intermediate dielectric layers stacked over the inner dielectric layer, the one or more intermediate vias being stacked over and electrically coupled with the inner via, wherein top surfaces of the one or more intermediate vias and top surfaces of the corresponding one or more intermediate dielectric layers are coplanar;
an outer via formed in an outer dielectric layer stacked over the one or more intermediate dielectric layers, the outer via being stacked over and electrically coupled with the one or more intermediate vias; and
a cover pad stacked over and electrically coupled with the outer via,
wherein the stack layer structure comprises a first via and a second via stacked over the first via, the first via being the inner via or one of the one or more intermediate vias, and the second via being one of the one or more intermediate vias or the outer via,
wherein a top width the first via is wider than a bottom width of the second via,
wherein a recess is formed in the first via to partially extend into a top surface thereof, and
wherein a bottom portion of the second via is within the recess, the bottom portion of the second via extending from a bottom surface thereof up to a height equal to a depth of the recess, the second via being in contact with the first via within the recess.

12. The stack layer structure of claim 11 ,
wherein the first via is tapered such that the top width thereof is wider than a bottom width thereof,
wherein the second via is tapered such that a top width thereof is wider than the bottom width thereof, and
wherein the recess is tapered such that a top width thereof is wider than a bottom width thereof.

13. The stack layer structure of claim 11 , wherein
a side surface of the bottom portion of the second via is in contact with a side surface of the recess, and
a bottom surface of the bottom portion of the second via is in contact with a bottom surface of the recess.

14. The stack layer structure of claim 11 , wherein there is no capture pad between the first via and the second via.

15. The stack layer structure of claim 11 , wherein the second via is electrically coupled with another via at a same layer through a pattern line, the second via being in contact with the pattern line.

16. The stack layer structure of claim 11 , further comprising:
a cover layer stacked over the outer dielectric layer, the cover layer being an outermost layer of the stack layer structure,
wherein the cover pad is formed in the cover layer and is configured to enable a signal connection with an external device.

17. The stack layer structure of claim 11 , wherein between the first via and the second via, the capture pad is electrically coupled to the cover pad through the first via and the second via in that order.

18. The stack layer structure of claim 11 , wherein the first via is formed from copper (Cu), the second via is formed from copper (Cu), or both.

19. The stack layer structure of claim 11 , wherein the depth of the recess ranges between 5% and 15% of a height of the first via.

20. The stack layer structure of claim 11 , further comprising:
an initial layer stacked below the inner dielectric layer,
wherein the capture pad is on and in contact with the initial layer.

21. The stack layer structure of claim 20 ,
wherein the capture pad, the inner via, the inner dielectric layer, the one or more intermediate vias, the one or more intermediate dielectric layers, the outer via, the outer dielectric layer, and the cover pad are formed above the initial layer,
wherein the stack layer structure further comprises:
a lower capture pad and a lower inner via formed in a lower inner dielectric layer stacked below the initial layer, the lower inner via being stacked below and electrically coupled with the lower capture pad;
one or more lower intermediate vias formed in corresponding one or more lower intermediate dielectric layers stacked be

Assignees

• Qualcomm Inc

Inventors

• We Hong Bok
• Buot Joan Rey Villarba
• Patil Aniket

Classifications

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title