Method of manufacturing through silicon via stacked structure

Patent metadata

Field	Value
Publication number	US-9536785-B2
Application number	US-201514963252-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Oct 25, 2012
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate.

First claim

What is claimed is:

1. A method of manufacturing through silicon via stacked structure, comprising:
providing a plurality of substrates, each having at least one via hole;
filling up said via hole with a dielectric material in an upper portion of said substrate;
forming at least one tapered hole in an upper portion of said dielectric material;
filling up each said tapered hole with a tapered through silicon via conductor;
forming a recessed portion on the wider end of each said tapered through silicon via conductor;
removing a part of said substrate until the narrower end of each said tapered through silicon via conductor protrudes from the other surface of said substrate;
forming a bump of conductive material on said protruding narrower end of each said tapered through silicon via conductor; and
stacking said plurality of substrates one on another by inserting said narrower end of each said tapered through silicon via conductor into a corresponding said recessed portion of said tapered through silicon via conductor of an adjoining and lower located one of said substrate.

2. The method of manufacturing through silicon via stacked structure according to claim 1 , further comprising covering one surface of each of said substrate with a dielectric layer.

3. The method of manufacturing through silicon via stacked structure according to claim 1 , further comprising covering one surface of each of said substrate with a non-conductive film.

4. The method of manufacturing through silicon via stacked structure according to claim 1 , wherein said recessed portion on said wider end of each said tapered through silicon via conductor is formed by a photolithographic process and an etching process.

5. The method of manufacturing through silicon via stacked structure according to claim 1 , wherein the step of removing a part of said substrate until the narrower end of each said tapered through silicon via protrudes from the other surface of said substrate is made by performing a selective etching process.

Assignees

• Nanya Technology Corp

Inventors

• Lin Po-Chun

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W90/00

  Package configurations · CPC title