Read error recovery

Patent metadata

Field	Value
Publication number	US-11314425-B2
Application number	US-201917051961-A
Country	US
Kind code	B2
Filing date	May 7, 2019
Priority date	May 8, 2018
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system and performing error recovery for the set of CWs using a set of error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure. The error recovery can include determining if each CW of the set of CWs is correctable by an EH step, storing indications of CWs determined correctable by the EH step in the error recovery data structure, determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

First claim

What is claimed is:

1. A system comprising:
a storage system comprising control circuitry and a memory array having multiple groups of memory cells,
wherein the control circuitry is configured to:
maintain an error recovery data structure in the storage system for a set of codewords (CWs) associated with one or more memory operations; and
perform error recovery for the set of CWs using a set of multiple error handling (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure, the error recovery comprising:
determine if each CW of the set of CWs is correctable by a specific EH step;
store indications of the CWs determined correctable by the specific EH step in the error recovery data structure;
determine if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure; and
in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, increment the specific EH step.

2. The system of claim 1 , wherein, to increment the specific EH step, the control circuitry is configured to:
determine if each CW of the set of CWs is correctable by the incremented EH step;
store indications of the CWs determined correctable by the incremented EH step in the error recovery data structure; and
determine if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure; and
in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, increment the incremented EH step.

3. The system of claim 1 , wherein, to perform error recovery for the set of CWs, the control circuitry is configured to perform error recovery using a first EH step from the set of EH steps,
wherein, to determine if each CW of the set of CWs is correctable by the EH step, the control circuitry is configured to determine if each CW of the set of CWs is correctable by the first EH step,
wherein, to store the indications of the CWs determined correctable by the EH step in the error recovery data structure, the control circuitry is configured to store indications of the CWs determined correctable by the first EH step in the error recovery data structure, and
wherein, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, the control circuitry is configured to increment the first EH step to a second EH step.

4. The system of claim 1 , wherein, to maintain the error recovery data structure, the control circuitry is configured to initialize the error recovery data structure having an entry for each CW of the set of CWs to an initial value, and
wherein, to store indications of the CWs determined correctable by the specific EH step, the control circuitry is configured to update values for each CW of the set of CWs in the error recovery data structure.

5. The system of claim 1 , wherein the control circuitry is configured to perform memory operations,
wherein, in performing one or more memory operations, the control circuitry is configured to detect one or more errors in one or more CWs stored in the memory array, and
wherein the set of CWs comprises CWs having one or more detected errors.

6. The system of claim 1 , wherein the error recovery data structure includes a bitmap having a single value for each of the set of CWs.

7. The system of claim 1 , wherein the storage system comprises one or more buffers configured to store corrected CWs, and
wherein the control circuitry is configured to transfer CWs determined correctable by the specific EH step to the one or more buffers.

8. The system of claim 7 , wherein the control circuitry is configured to remove CWs determined correctable by the specific EH step from the set of CWs.

9. The system of claim 1 , wherein the control circuitry is configured to perform each step in the order presented.

10. A method comprising:
maintaining, using control circuitry of a storage system, an error recovery data structure in the storage system for a set of codewords (CWs) associated with one or more memory operations of the storage system;
performing error recovery for the set of CWs using a set of multiple error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure, wherein performing error recovery comprises:
determining, for a first EH step of the set of multiple EH steps, if each CW of the set of CWs is correctable by the first EH step;
storing indications of CWs determined correctable by the first EH step in the error recovery data structure;
determining if one or more ON in the set of CWs are not indicated as correctable in the error recovery data structure;
in response to the determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the first EH step to a second EH step of the set of multiple EH steps;
determining, for the second EH step, if each CW of the set of CWs is correctable by the first EH step; and
storing indications of CWs determined correctable by the first or second EH steps in the error recovery data structure.

11. The method of claim 10 , wherein maintaining the error recovery data structure comprises initializing the error recovery data structure having an entry for each CW of the set of CWs to an initial value, and
wherein storing indications of the CWs determined correctable by the specific EH step comprise updating the initial values for each CW of the set of CWs in the error recovery data structure.

12. The method of claim 10 , comprising:
detecting one or more errors in one or more CWs stored in the storage system,
wherein maintaining the error recovery data structure comprises maintaining an error recovery bitmap having a single value for each of a set of CWs having one or more detected errors.

13. The method of claim 10 , wherein the error recovery data structure includes a bitmap having a single value for each of the set of CWs.

14. The method of claim 10 , comprising transferring CWs determined correctable by the set of EH step to one or more buffers of the storage system.

15. The method of claim 14 , comprising removing CWs determined correctable by the set of EH step from the set of CWs.

16. A non-transitory device-readable storage medium comprising instructions that, when executed by controller circuitry of a storage system, cause the storage system to perform operations comprising:
maintaining, an error recovery data structure in the storage system for a set of codewords (CWs) associated with one or more memory operations of the storage system;
performing error recovery for the set of CWs using a set of multiple error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure, wherein performing error recovery comprises:
determining, for a first EH step of the set of multiple EH steps, if each CW of the set of CWs is correctable by the first EH step;
storing indications of CWs determined correctable by the first EH step in the error recovery data structure;
determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure;
in response to the determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the first EH step to a second EH step of the set of multiple EH steps;
det

Assignees

• Micron Technology Inc

Inventors

• Luo Xiangang
• Singidi Harish Reddy
• Luo Ting
• Muchherla Kishore Kumar

Classifications

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title