Additive manufacturing process of 3D electronic substrate

Patent metadata

Field	Value
Publication number	US-12226822-B2
Application number	US-202318448311-A
Country	US
Kind code	B2
Filing date	Aug 11, 2023
Priority date	Oct 10, 2018
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

A method of forming electronic substrates and assemblies is provided. The method includes forming a first layer, including co-depositing a first material and a second material, where the first material and the second material are co-deposited as powders, binders, slurries, inks, or combinations thereof, and at least partially sintering or curing the first layer of co-deposited materials. Further, the method includes forming a second layer, including co-depositing the first material and the second material, and at least partially sintering or curing the second layer of co-deposited materials. Additionally, the method includes retrieving a solid electronic substrate wherein the sintered or cured first material of the first layer forms the solid electronic substrate and the sintered or cured second material of the first layer forms a feature in or on the solid electronic substrate.

First claim

What is claimed is:

1. A method of forming a solid electronic substrate, the method comprising:
forming a first layer, wherein forming the first layer comprises co-depositing an electrically insulative first material and an electrically conductive second material, wherein the electrically insulative first material and the electrically conductive second material are co-deposited as powders, binders, slurries, inks, or combinations thereof to form the first layer, and wherein at least one of the electrically insulative first material or the electrically conductive second material comprises a powder that is deposited and then subjected to compaction;
at least partially sintering or curing the first layer of co-deposited materials;
forming a second layer, wherein forming the second layer comprises co-depositing the electrically insulative first material and the electrically conductive second material, wherein the electrically insulative first material and the electrically conductive second material of the second layer are co-deposited as powders, binders, slurries, inks, or combinations thereof to form the second layer, and wherein the second layer is co-deposited on top of and contiguous with the at least partially sintered or cured first layer of co-deposited materials;
at least partially sintering or curing the second layer of co-deposited materials; and
retrieving a solid electronic substrate, wherein the sintered or cured electrically insulative first material of the first layer forms the solid electronic substrate, and the sintered or cured electrically conductive second material of the first layer forms a feature in or on the solid electronic substrate, and wherein the solid electronic substrate includes at least one feature positioned on at least three sides of the solid electronic substrate.

2. The method of claim 1 , wherein the electrically conductive second material includes one of metal particles, an oxide, a boride, a phosphide, a carbide, and a metal-organic compound that increases a catalytic activity of the solid electronic substrate.

3. The method of claim 1 , wherein the electrically conductive second material includes metal particles of one of ruthenium, rhodium, palladium, rhenium, platinum, osmium, iridium, gold, and silver.

4. The method of claim 1 , wherein the electrically conductive second material includes an oxide of one of ruthenium (IV) oxide, rhodium (III) oxide, palladium (II) oxide, rhenium (VI) oxide, and platinum (IV) oxide.

5. The method of claim 1 , wherein the electrically conductive second material includes a metal-organic compound including one of ruthenium, rhodium, palladium, rhenium, platinum, osmium, iridium, gold, and silver.

6. The method of claim 1 , wherein forming the first layer further comprises:
co-depositing a third material with the electrically insulative first material and the electrically conductive second material, wherein the electrically insulative first material, the electrically conductive second material, and the third material of the first layer are co-deposited as powders, binders, slurries, inks, or combinations thereof to form the first layer, and wherein the third material is one of metal particles, an oxide, a boride, a phosphide, a carbide, and a metal-organic compound that increases a catalytic activity of the solid electronic substrate.

7. The method of claim 6 , wherein forming the second layer further comprises:
co-depositing the third material with the electrically insulative first material and the electrically conductive second material, wherein the electrically insulative first material, the electrically conductive second material, and the third material of the second layer are co-deposited as powders, binders, slurries, inks, or combinations thereof to form the second layer.

8. The method of claim 6 , wherein the third material includes the metal particles of one of ruthenium, rhodium, palladium, rhenium, platinum, osmium, iridium, gold, and silver.

9. The method of claim 6 , wherein the third material includes the oxide of one of ruthenium (IV) oxide, rhodium (III) oxide, palladium (II) oxide, rhenium (VI) oxide, and platinum (IV) oxide.

10. The method of claim 6 , wherein the third material includes the metal-organic compound including one of ruthenium, rhodium, palladium, rhenium, platinum, osmium, iridium, gold, and silver.

11. The method of claim 6 , wherein the electrically insulative first material, the electrically conductive second material, and the third material of the first layer include a mixture of at least three powders, binders, slurries, or inks having different melting points, and wherein the at least partially sintering includes transient liquid-phase sintering.

12. The method of claim 1 , wherein the method further comprises completing the sintering or curing process for at least the first layer and the second layer.

13. The method of claim 1 , wherein the solid electronic substrate is in the shape of a regular polygon, an irregular polygon, or a cylinder.

14. The method of claim 1 , wherein the electrically conductive second material of the first layer is a conductive material that, when sintered, forms a signal trace in or on the solid electronic substrate, a twisted wire pair, coaxial cable, or other wire.

15. The method of claim 1 , wherein the electrically conductive second material of the first layer, when sintered, forms a thermal sensor in or on the solid electronic substrate, an antenna in or on the solid electronic substrate, a contact pad in or on the solid electronic substrate, or a via within the solid electronic substrate.

16. The method of claim 1 , wherein the electrically insulative first material of the first layer is a ceramic material.

17. A method comprising:
deploying the solid electronic substrate formed in accordance with claim 1 in a downhole well.

Assignees

• Schlumberger Technology Corp

Inventors

• Dunford Steven O
• Kostinovsky Mark

Classifications

• B22F12/58

  for changing the material composition, e.g. by mixing · CPC title

• B22F1/09

  Mixtures of metallic powders · CPC title

• B22F10/28

  Powder bed fusion, e.g. selective laser melting [SLM] or electron beam melting [EBM] · CPC title

• H05K3/1241

  by ink-jet printing or drawing by dispensing · CPC title

• H05K3/4664

  Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders (H05K3/4647 takes precedence) · CPC title