PGaN enhancement mode HEMTs with dopant diffusion spacer

Patent metadata

Field	Value
Publication number	US-12224337-B2
Application number	US-202017132951-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

First claim

What is claimed is:

1. A Group III-nitride (III-N) transistor, comprising:
a channel layer comprising a first III-N material;
a polarization layer over the channel layer, wherein the polarization layer is a second III-N material with more Al than the first III-N material;
a p-type layer over the polarization layer, wherein the p-type layer is a third III-N material comprising a greater concentration of a P-type impurity than either the channel layer or the polarization layer;
a spacer layer between, and in contact with, the polarization layer and the p-type layer, wherein the spacer layer is the third III-N material, but with a lower concentration of the P-type impurity than the p-type layer;
a gate terminal over the spacer layer; and
source and drain terminals coupled to the channel layer.

2. The III-N transistor of claim 1 , wherein:
the P-type impurity comprises Mg;
a concentration of Mg within the p-type layer is at least 1e19 atoms/cm 3 ; and
the spacer layer has thickness of at least 2 nm.

3. The III-N transistor of claim 2 , wherein:
the spacer layer has a thickness of less than 10 nm; and
the p-type layer has a thickness of at least 5 nm.

4. The III-N transistor of claim 1 , wherein:
the p-type layer has thickness of 5-20 nm; and
a concentration of the P-type impurity within the spacer layer is at least an order of magnitude lower than within the p-type layer.

5. The III-N transistor of claim 1 , wherein the spacer layer and the p-type layer both comprise less Al than the polarization layer.

6. The III-N transistor of claim 1 , wherein:
the first III-N material is a binary alloy of Ga and N;
the third III-N material is a binary alloy of Ga and N;
and
the second III-N material is a ternary alloy of Al, Ga and N.

7. The III-N transistor of claim 6 , wherein:
the polarization layer has a thickness of 5-15 nm; and
the channel layer has a thickness of at least 50 nm.

8. The III-N transistor of claim 1 , wherein a concentration of the P-type impurity within the polarization layer is no more than 1e18 atoms/cm 3 .

9. The III-N transistor of claim 8 , wherein the P-type impurity is Mg and a concentration of Mg within the polarization layer is no more than 1e17 atoms/cm 3 .

10. The III-N transistor of claim 1 , further comprising a dielectric material between the p-type layer and the gate terminal.

11. A system comprising:
a power supply; and
a radio transceiver electrically coupled to the power supply, wherein at least one of the power supply and the radio transceiver comprise a Group III-nitride (III-N) transistor, and
wherein the III-N transistor comprises:
a channel layer comprising a first Group III-nitride (III-N) material;
a polarization layer over the channel layer, wherein the polarization layer comprises a second III-N material with more Al than the first III-N material;
a p-type layer over the polarization layer, wherein the p-type layer is a binary alloy of Ga and N comprising Mg;
a spacer layer between the polarization layer and the p-type layer, wherein the spacer layer is in contact with the p-type layer and is a binary alloy of Ga and N that has a lower concentration of Mg than the p-type layer;
a gate terminal over the spacer layer; and
source and drain terminals coupled to the channel layer.

12. The system of claim 11 , wherein:
the channel layer has a thickness of at least 50 nm and consists essentially of Ga and N;
the spacer layer has a thickness of 2-10 nm and consists essentially of Ga and N;
the p-type layer has a thickness of at least 5 nm and consists essentially of Ga and N with a concentration of Mg of at least 1e19 atoms/cm 3 ; and
the polarization layer is 5-15 nm of Al x Ga 1x N with a concentration of Mg no more than 1e18 atoms/cm 3 .

13. The system of claim 11 , further comprising a battery coupled to the power supply.

14. The system of claim 11 , wherein the radio transceiver comprises a power amplifier on a transmit path and a low noise amplifier on a receive path, at least one of which comprises the III-N transistor.

15. An apparatus, comprising:
a transistor channel layer comprising a first III-N material;
a polarization layer over the channel layer, wherein the polarization layer comprises a second III-N material with more Al than the first III-N material;
a p-type layer over the polarization layer, wherein the p-type layer has a thickness of at least 5 nm and comprises a III-N material comprising a P-type impurity at a concentration of at least 1e19 atoms/cm 3 ;
a spacer layer between the polarization layer and the p-type layer, wherein the spacer layer has a thickness of 2-10 nm and comprises a III-N material with a lower concentration of the P-type impurity than the p-type layer;
a transistor gate terminal over the spacer layer; and
transistor source and drain terminals coupled to the transistor channel layer.

16. The apparatus of claim 15 , wherein the spacer layer is a binary alloy of Ga and N.

17. The apparatus of claim 16 , wherein the p-type layer is a binary alloy of Ga and N.

18. The apparatus of claim 15 , wherein a concentration of the P-type impurity within the polarization layer is no more than 1e18 atoms/cm 3 , and wherein the concentration of the P-type impurity within the spacer layer is between the concentration of the P-type impurity within the p-type layer and the concentration of the P-type impurity within the polarization layer.

19. The apparatus of claim 15 , wherein the spacer layer is in direct contact with the p-type layer.

20. The apparatus of claim 19 , wherein the spacer layer is in direct contact with the polarization layer.

Assignees

• Intel Corp

Inventors

• Beumer Michael
• Ehlert Robert
• Minutillo Nicholas
• Robinson Michael
• Wallace Patrick
• Wells Peter

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title

• H10D30/475 Primary

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title