III-nitride devices including a graded depleting layer

Patent metadata

Field	Value
Publication number	US-10224401-B2
Application number	US-201715564498-A
Country	US
Kind code	B2
Filing date	May 31, 2017
Priority date	May 31, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

First claim

What is claimed is:

1. A III-N device comprising:
a III-N layer structure comprising
a III-N channel layer,
a 2DEG channel in, and a III-N barrier layer over, the III-N channel layer, and
a graded III-N layer over the III-N barrier layer, the graded III-N layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side;

a first power electrode and a second power electrode; and
a gate between the first power electrode and the second power electrode, the gate being over the III-N layer structure;
wherein a composition of the graded III-N layer is graded such that a bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side;
wherein the graded III-N layer includes a device access region that is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode;
wherein the III-N device has a threshold voltage and
wherein the III-N device is configured such that
when the gate is biased relative to the first power electrode at a voltage greater than the threshold voltage, the 2DEG channel extends continuously from the first power electrode to the second power electrode and
when the gate is biased relative to the first power electrode at a voltage less than the threshold voltage and the second power electrode is biased relative to the first power electrode at a positive voltage that is less than a minimum voltage, the 2DEG is depleted of mobile charge in a gate region of the III-N device.

2. The III-N device of claim 1 , wherein the III-N device is configured such that when the gate is biased relative to the first power electrode at a voltage less than the threshold voltage and the second power electrode is biased relative to the first power electrode at a positive voltage that is greater than the minimum voltage, the 2DEG is depleted of mobile charge in the device access region between the gate and the second power electrode.

3. The III-N device of claim 2 , wherein the minimum voltage is 5V or larger.

4. The III-N device of claim 2 , wherein the minimum voltage is in a range of 5V to 100V.

5. A III-N device comprising:
a III-N layer structure comprising
a III-N channel layer,
a 2DEG channel in, and a III-N barrier layer over, the III-N channel layer, and
a graded III-N layer over the III-N barrier layer, the graded III-N layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side;

a first power electrode and a second power electrode; and
a gate between the first power electrode and the second power electrode, the gate being over the III-N layer structure;
wherein a composition of the graded III-N layer is graded such that a bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side;
wherein the graded III-N layer includes a device access region that is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode; and
wherein a grading profile of the graded III-N layer is such that a polarization charge density in the graded III-N layer is in a range of 10-100% of an areal sheet charge density of mobile charge in the 2DEG channel.

6. The III-N device of claim 5 , the III-N device having a threshold voltage, wherein a grading profile of the graded III-N layer is such that mobile charge in the 2DEG channel in the device access region between the gate and the second power electrode is depleted while the gate is biased relative to the first power electrode at a voltage lower than the threshold voltage and the second power electrode is biased above a minimum voltage relative to the first power electrode, but not depleted while the gate is biased relative to the first power electrode at a voltage higher than the threshold voltage.

7. The III-N device of claim 5 , further comprising a recess extending through the graded III-N layer, wherein the gate is in the recess.

8. The III-N device of claim 5 , further comprising a field plate which is connected to the first power electrode and directly contacts a surface of the graded III-N layer that is between the gate and the second power electrode.

9. The III-N device of claim 5 , the III-N device having a threshold voltage, wherein a grading profile of the graded III-N layer is such that mobile charge in the 2DEG channel in the device access region between the gate and the second power electrode is depleted while the gate is biased relative to the first power electrode at a voltage lower than the threshold voltage and the second power electrode is biased above a minimum voltage relative to the first power electrode, but not depleted while the gate is biased relative to the first power electrode at a voltage lower than the threshold voltage and the second power electrode is biased below the minimum voltage relative to the first power electrode.

10. The III-N device of claim 9 , wherein the minimum voltage is in a range of 5V to 100V.

11. A III-N device comprising: of claim 1 ,
a III-N layer structure comprising
a III-N channel layer,
a III-N barrier layer over the III-N channel layer, and
a graded III-N layer over the III-N barrier layer, the graded III-N layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side;

a first power electrode and a second power electrode; and
a gate between the first power electrode and the second power electrode, the gate being over the III-N layer structure;
wherein a composition of the graded III-N layer is graded such that a bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side;
wherein the graded III-N layer includes a device access region that is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode; and
wherein the graded III-N layer comprises a first graded III-N layer adjacent to the first side and a second graded III-N layer adjacent to the second side, wherein the first graded III-N layer is thicker than the second graded III-N layer.

12. The III-N device of claim 11 , wherein the first graded III-N layer is at least three times thicker than the second graded III-N layer.

13. The III-N device of claim 11 , wherein a bandgap of the first graded III-N layer is graded at a first rate, and a bandgap of the second graded III-N layer is graded at a second rate, the second rate being greater than the first rate.

14. The III-N device of claim 13 , wherein the second rate is at least five times greater than the first rate.

15. A transistor comprising:
a III-N layer structure comprising a III-N channel layer, a III-N barrier layer over the III-N channel layer, a first graded III-N layer over the III-N barrier layer, and a second graded III-N layer over the first graded III-N layer, the second graded III-N layer being thinner than the first graded III-N layer;
a source electrode and a drain electrode;
a gate between the source electrode and the drain electrode, the gate being over the III-N layer structure; and
a field plate that is electrically connected to the source electrode and contacts a surface of the second graded III-N layer between the gate and the drain electrode; wherein
the first graded III-N lay

Assignees

• Transphorm Inc

Inventors

• Mishra Umesh
• Lal Rakesh K
• Gupta Geetak
• Neufeld Carl Joseph
• Rhodes David

Classifications

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H01L29/4236

  Electricity · mapped topic

• H01L29/0688 Primary

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic

• H01L29/7786

  Electricity · mapped topic