Magnetic core inductors in interposer

Patent metadata

Field	Value
Publication number	US-12224252-B2
Application number	US-202017030121-A
Country	US
Kind code	B2
Filing date	Sep 23, 2020
Priority date	Sep 23, 2020
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.

First claim

What is claimed is:

1. A coreless interposer, comprising:
a plurality of buildup layers, wherein electrical routing is provided in the plurality of buildup layers; and
an inductor embedded in the plurality of buildup layers, wherein the inductor comprises:
a plurality of discrete magnetic shells; and
a conductive lining over an interior surface of each of the plurality of discrete magnetic shells.

2. The coreless interposer of claim 1 , wherein the inductor extends through two or more of the plurality of buildup layers.

3. The coreless interposer of claim 1 , wherein a first end of the inductor is below a topmost buildup layer, and wherein a second end of the inductor is above a bottommost buildup layer.

4. The coreless interposer of claim 1 , further comprising:
a second inductor embedded in the plurality of buildup layers, wherein the second inductor comprises:
a second magnetic shell; and
a second conductive lining over an interior surface of the second magnetic shell.

5. The coreless interposer of claim 4 , wherein a first end of the inductor is electrically coupled to a first end of the second inductor by a trace.

6. The coreless interposer of claim 1 , wherein a first end of the inductor is electrically coupled to a pad on a topmost surface of the plurality of buildup layers by one or more vias.

7. The coreless interposer of claim 1 , further comprising:
a second conductive lining over an interior surface of each of the plurality of discrete magnetic shells, wherein the conductive lining and the second conductive lining are coupled together by a corresponding one of the plurality of discrete magnetic shells.

8. The coreless interposer of claim 1 , further comprising:
a plug within the conductive lining.

9. The coreless interposer of claim 1 , further comprising:
a coreless package coupled to the coreless interposer; and
a die coupled to the coreless package.

10. A coreless interposer, comprising:
a plurality of buildup layers wherein electrical routing is provided in the plurality of buildup layers;
an inductor embedded in the plurality of buildup layers, wherein the inductor comprises:
a first magnetic block;
a second magnetic block, wherein the second magnetic block is connected to the first magnetic block by a first magnetic lid;
a third magnetic block;
a fourth magnetic block, wherein the fourth magnetic block is connected to the third magnetic block by a second magnetic lid; and
a first plurality of conductive loops surrounding the second magnetic block; and
a second plurality of conductive loops surrounding the third magnetic block.

11. The coreless interposer of claim 10 , wherein the first plurality of conductive loops and the second plurality of conductive loops are disposed in more than one buildup layer of the plurality of buildup layers.

12. The coreless interposer of claim 10 , further comprising:
shielding layers over a first end and a second end of the inductor.

13. The coreless interposer of claim 10 , wherein the first plurality of conductive loops are electrically coupled to the second plurality of conductive loops.

14. The coreless interposer of claim 10 , wherein the first magnetic block, the second magnetic block, the third magnetic block, and the fourth magnetic block pass through two or more buildup layers.

15. The coreless interposer of claim 10 , wherein the first conductive loops and the second conductive loops are part of the electrical routing in the plurality of buildup layers.

16. The coreless interposer of claim 10 , wherein the first magnetic block, the second magnetic block, the third magnetic block, and the fourth magnetic block comprise a first row of magnetic blocks, and wherein the inductor further comprises at least a second row of magnetic blocks.

17. The coreless interposer of claim 16 , wherein the inductor further comprises:
a third plurality of conductive loops surrounding magnetic blocks in the second row of magnetic blocks; and
a fourth plurality of conductive loops surrounding magnetic blocks in the second row of magnetic blocks.

18. The coreless interposer of claim 10 , wherein the first magnetic block, the second magnetic block, the third magnetic block, and the fourth magnetic block are cylinders.

19. An electronic system, comprising:
a board;
a coreless interposer coupled to the board, wherein the coreless interposer comprises:
an embedded inductor, comprising a plurality of discrete magnetic shells with a conductive layer lining an interior surface of each of the plurality of discrete magnetic shells;

a coreless patch coupled to the coreless interposer; and
a die coupled to the coreless patch.

20. The electronic system of claim 19 , wherein the inductor is vertically oriented, and wherein the inductor passes through a plurality of buildup layers of the coreless interposer.

21. A coreless interposer, comprising:
a plurality of buildup layers, wherein electrical routing is provided in the plurality of buildup layers;
a first inductor embedded in the plurality of buildup layers, wherein the first inductor comprises:
a first magnetic shell; and
a first conductive lining over an interior surface of the first magnetic shell; and

a second inductor embedded in the plurality of buildup layers, wherein the second inductor comprises:
a second magnetic shell; and
a second conductive lining over an interior surface of the second magnetic shell.

22. The coreless interposer of claim 21 , wherein a first end of the first inductor is electrically coupled to a first end of the second inductor by a trace.

23. The coreless interposer of claim 21 , wherein each of the first inductor and the second inductor extends through two or more of the plurality of buildup layers.

24. The coreless interposer of claim 21 , wherein a first end of each of the first inductor and the second inductor is below a topmost buildup layer, and wherein a second end of each of the first inductor and the second inductor is above a bottommost buildup layer.

25. The coreless interposer of claim 21 , further comprising:
a first plug within the first conductive lining; and
a second plug within the second conductive lining.

Assignees

• Intel Corp

Inventors

• Bharath Krishna
• Lambert William J
• Hariri Haifa
• Kulasekaran Siddharth
• Manusharow Mathew
• Augustine Anne

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title