Memory device and manufacturing method of the memory device

Patent metadata

Field	Value
Publication number	US-12219761-B2
Application number	US-202117399892-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Feb 24, 2021
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.

First claim

What is claimed is:

1. A memory device comprising:
a first gate stack structure and a second gate stack structure; and
a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other,
wherein the slit includes a plurality of first holes extending in a vertical direction, and side portions of the plurality of first holes are connected to side portions of neighboring first holes.

2. The memory device of claim 1 ,
wherein, in the slit, the plurality of first holes are arranged in a line to be connected to each other, or the plurality of first holes are arranged in a zigzag shape to be connected to each other.

3. The memory device of claim 1 ,
wherein the first gate stack structure is formed within a first memory region, the second gate stack structure is formed within a second memory region, and the slit is formed within a slit region, and
wherein the slit region is disposed between the first memory region and the second memory region.

4. The memory device of claim 3 ,
wherein the first gate stack structure and the second gate stack structure include a plurality of plate electrodes and a plurality of interlayer insulating layers, which are alternately stacked.

5. The memory device of claim 4 ,
wherein the plurality of first holes electrically and physically isolate the plurality of plate electrodes of the first gate stack structure and the plurality of plate electrodes of the second gate stack structure from each other within the slit region.

6. The memory device of claim 4 ,
wherein the plurality of interlayer insulating layers of the first gate stack structure and the plurality of interlayer insulating layers of the second gate stack structure extend into the slit region to be connected to each other, and
wherein the plurality of first holes penetrate the plurality of interlayer insulating layers of the first gate stack structure and the plurality of interlayer insulating layers of the second gate stack structure within the slit region.

7. The memory device of claim 4 ,
wherein one end portions of the plate electrodes of the first gate stack structure, which are adjacent to the slit, have a first wave pattern.

8. The memory device of claim 7 ,
wherein one end portions of the plate electrodes of the second gate stack structure, which are adjacent to the slit, have a second wave pattern.

9. The memory device of claim 8 ,
wherein the first wave pattern and the second wave pattern are substantially symmetrical to each other.

10. The memory device of claim 1 , wherein each of the first gate stack structure and the second gate stack structure includes cell plugs extending in the vertical direction.

11. The memory device of claim 1 , further comprising a source line contact formed at the inside of the slit.

Assignees

• Sk Hynix Inc

Inventors

• Choi Won Geun
• Jang Jung Shik
• Kim Jang Won
• Park Mi Seong

Classifications

• H10W10/20

  Air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title