Nested interposer with through-silicon via bridge die

Patent metadata

Field	Value
Publication number	US-12218040-B2
Application number	US-202117186289-A
Country	US
Kind code	B2
Filing date	Feb 26, 2021
Priority date	Feb 26, 2021
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

First claim

What is claimed is:

1. An electronic package, comprising:
an interposer, wherein the interposer comprises:
an interposer substrate;
a cavity that passes into but not through the interposer substrate;
a through interposer via (TIV) within the interposer substrate;
an interposer pad electrically coupled to the TIV; and
a first backside pad coupled to the TIV;

a nested component in the cavity, wherein the nested component comprises a component pad coupled to a through-component via;
a core via beneath the nested component, the core via extending from the nested component through the interposer substrate to a second backside pad, the second backside pad laterally spaced apart from the first backside pad, and the second backside pad separate and distinct from the first backside pad; and
a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

2. The electronic package of claim 1 , wherein the first interconnect and the second interconnect each comprise:
an intermediate pad; and
a bump over the intermediate pad.

3. The electronic package of claim 2 , further comprising:
a dielectric layer over and around the interposer and the nested component.

4. The electronic package of claim 3 , wherein the intermediate pads are over a surface of the dielectric layer.

5. The electronic package of claim 4 , wherein the intermediate pad of the first interconnect is coupled to the interposer pad by a first via that passes through a portion of the dielectric layer, and wherein the intermediate pad of the second interconnect is coupled to the component pad by a second via that passes through a portion of the dielectric layer.

6. The electronic package of claim 4 , wherein the intermediate pad of the first interconnect is directly connected to the interposer pad, and wherein the intermediate pad of the second interconnect is directly connected to the component pad.

7. The electronic package of claim 1 , wherein a centerline of the first interconnect is offset from a centerline of the interposer pad, and wherein a centerline of the second interconnect is offset from a centerline of the component pad.

8. The electronic package of claim 1 , wherein a first portion of the cavity is within a footprint of the die, and wherein a second portion of the cavity is outside of the footprint of the die.

9. The electronic package of claim 1 , wherein the nested component is an active component.

10. The electronic package of claim 1 , further comprising:
a second die, wherein the second die is coupled to the nested component by a third interconnect comprising:
an intermediate pad; and
a bump over the intermediate pad.

11. The electronic package of claim 10 , wherein the nested component electrically couples the first die to the second die.

12. The electronic package of claim 1 , wherein an active surface of the nested component faces towards the die.

13. The electronic package of claim 1 , wherein the interposer substrate comprises glass, ceramic, silicon, silicon carbide, alumina, or organic materials.

14. An electronic system, comprising:
a board;
an interposer electrically coupled to the board, wherein the interposer comprises a cavity that passes into but not through an interposer substrate, a nested component in the cavity, a through interposer via (TIV) within the interposer substrate and coupled to a first backside pad, and a core via beneath the nested component, the core via extending from the nested component through the interposer substrate to a second backside pad, the second backside pad laterally spaced apart from the first backside pad, and the second backside pad separate and distinct from the first backside pad;
a first die electrically coupled to the interposer and the nested component by a first plurality of interconnects; and
a second die electrically coupled to the interposer and the nested component by a second plurality of interconnects.

15. The electronic system of claim 14 , wherein the nested component electrically couples the first die to the second die.

16. The electronic system of claim 14 , further comprising:
a package substrate, wherein the package substrate is electrically coupled to the board, and wherein the interposer is electrically coupled to the package substrate.

17. An electronic package, comprising:
an interposer, wherein the interposer comprises:
a glass substrate;
a cavity that passes into but not through the glass substrate;
a through glass via (TGV) within the glass substrate;
an interposer pad electrically coupled to the TGV; and
a first backside pad coupled to the TIV;

a silicon bridge die in the cavity, wherein the silicon bridge die comprises a silicon bridge die pad coupled to a through-silicon via;
a core via beneath the silicon bridge die, the core via extending from the silicon bridge die through the glass substrate to a second backside pad, the second backside pad laterally spaced apart from the first backside pad, and the second backside pad separate and distinct from the first backside pad; and
a die coupled to the interposer pad by a first interconnect and coupled to the silicon bridge die pad by a second interconnect.

18. The electronic package of claim 17 , wherein the first interconnect and the second interconnect each comprise:
an intermediate pad; and
a bump over the intermediate pad.

19. The electronic package of claim 18 , further comprising:
a dielectric layer over and around the interposer and the silicon bridge die.

20. The electronic package of claim 19 , wherein the intermediate pads are over a surface of the dielectric layer.

21. The electronic package of claim 20 , wherein the intermediate pad of the first interconnect is coupled to the interposer pad by a first via that passes through a portion of the dielectric layer, and wherein the intermediate pad of the second interconnect is coupled to the silicon bridge die pad by a second via that passes through a portion of the dielectric layer.

22. The electronic package of claim 20 , wherein the intermediate pad of the first interconnect is directly connected to the interposer pad, and wherein the intermediate pad of the second interconnect is directly connected to the silicon bridge die pad.

23. The electronic package of claim 17 , wherein a centerline of the first interconnect is offset from a centerline of the interposer pad, and wherein a centerline of the second interconnect is offset from a centerline of the silicon bridge die pad.

24. The electronic package of claim 17 , wherein a first portion of the cavity is within a footprint of the die, and wherein a second portion of the cavity is outside of the footprint of the die.

25. The electronic package of claim 17 , further comprising:
a second die, wherein the second die is coupled to the silicon bridge die by a third interconnect comprising:
an intermediate pad; and
a bump over the intermediate pad.

Assignees

• Intel Corp

Inventors

• Pietambaram Srinivas V
• Mallik Debendra
• Darmawikarta Kristof
• Mahajan Ravindranath V
• Manepalli Rahul N

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title