Method for constructing a solenoid inductor

Patent metadata

Field	Value
Publication number	US-12217898-B2
Application number	US-202318383816-A
Country	US
Kind code	B2
Filing date	Oct 25, 2023
Priority date	Mar 13, 2020
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

A method for constructing a solenoid inductor of an IC package with active/passive devices includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.

First claim

The invention claimed is:

1. A method for constructing a solenoid inductor, comprising:
positioning an inner winding substantially around a magnetic core;
positioning an outer winding substantially around the inner winding; and
using a layered process to perform said positioning the inner and outer windings;
wherein said using the layered process comprises:
processing a first conducting layer that is a bottom layer of the outer winding;
processing a first dielectric layer above the first conducting layer;
processing a second conducting layer above the first dielectric layer that is a bottom layer of the inner winding;
processing a second dielectric layer above the second conducting layer;
processing a magnetic core layer above the second dielectric layer;
processing a third dielectric layer above the magnetic core layer;
processing a third conducting layer above the third dielectric layer that is a top layer of the inner winding;
processing a fourth dielectric layer above the third conducting layer;
processing a fourth conducting layer above the fourth dielectric layer that is a top layer of the outer winding; and
processing a fifth dielectric layer above the fourth conducting layer;

wherein the inner and outer windings are electrically connected; and
wherein the solenoid inductor is constructed as a component of an integrated circuit package with one or more active or passive devices.

2. The method of claim 1 , wherein said using the layered process further comprises:
processing vertical conductors through the first, second, third and fourth dielectric layers to electrically connect the bottom and top layers of the outer winding; and
processing vertical conductors through the second and third dielectric layers to electrically connect the bottom and top layers of the inner winding.

3. The method of claim 2 , wherein said using the layered process further comprises:
for each conducting layer of the first, second, third and fourth conducting layers:
separating the conducting layer into multiple conductors;
wherein said processing vertical conductors through the first, second, third and fourth dielectric layers to electrically connect the bottom and top layers of the outer winding comprises electrically connecting corresponding ones of the multiple conductors of the bottom and top layers of the outer winding to form corresponding turns of the outer winding; and
wherein said processing the vertical conductors through the second and third dielectric layers to electrically connect the bottom and top layers of the inner winding comprises electrically connecting corresponding ones of the multiple conductors of the bottom and top layers of the inner winding to form corresponding turns of the inner winding.

4. The method of claim 1 , wherein the inner and outer windings are electrically connected serially to generate non-opposing magnetic fields in the magnetic core.

5. The method of claim 4 , further comprising:
positioning additional windings substantially around the inner and outer windings using the layered process;
wherein each successive additional winding of the additional windings is substantially positioned around previous additional windings; and
wherein the inner and outer and additional windings are electrically connected serially and in a manner such as to generate non-opposing magnetic fields in the magnetic core.

6. The method of claim 1 , wherein the inner and outer windings are electrically connected to generate opposing magnetic fields in the magnetic core.

7. The method of claim 6 , wherein the inner and outer windings have different numbers of turns.

8. The method of claim 7 , wherein the different numbers of turns provide substantially matching respective inductance values of the inner and outer windings.

9. The method of claim 6 , further comprising:
positioning an even number of additional windings substantially around the inner and outer windings using the layered process;
wherein each successive additional winding of the additional windings is substantially positioned around previous additional windings; and
wherein the inner and outer windings and additional windings are electrically connected in a manner such that an outer half of all the windings layers generate magnetic fields in the magnetic core that oppose magnetic fields generated in the magnetic core by an inner half of all the windings layers.

10. The method of claim 6 , wherein the inner and outer windings have identical numbers of turns.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Khenkin Aleksey
• Patten David
• Yan Jun

Classifications

• H01F41/08

  Winding conductors onto closed formers or cores, e.g. threading conductors through toroidal cores · CPC title

• H01F27/24

  Magnetic cores · CPC title

• H01F17/0013 Primary

  with stacked layers · CPC title

• H01F2017/0086

  on semiconductor substrate · CPC title

• H01F2017/0066

  with a magnetic layer · CPC title