Integrated magnetic core inductor and methods of fabrications thereof

Patent metadata

Field	Value
Publication number	US-9799721-B2
Application number	US-201514689494-A
Country	US
Kind code	B2
Filing date	Apr 17, 2015
Priority date	Apr 17, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A method of forming a semiconductor device includes forming a lower coil segment in a first dielectric layer over a substrate, forming a second dielectric layer over the lower coil segment and the first dielectric layer, anisotropically etching a top portion of the second dielectric layer to form an opening over the lower coil segment, depositing magnetic material in the opening to form a magnetic core, forming a third dielectric layer over the magnetic core and the second dielectric layer, forming vias extending through the second dielectric layer and the third dielectric layer, and after forming the vias, forming an upper coil segment over the third dielectric layer and the magnetic core, wherein the vias connect the upper coil segment with the lower coil segment.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming a lower coil segment in a first dielectric layer over a substrate;
forming a second dielectric layer over the lower coil segment and the first dielectric layer;
anisotropically etching a top portion of the second dielectric layer to form an opening over the lower coil segment;
depositing magnetic material in the opening to form a magnetic core, comprising:
repeatedly depositing a film structure in the opening to form a laminated structure for the magnetic core, wherein the film structure is formed by depositing a first layer made of a first metal, a second layer over the first layer made of an oxide of a second metal, a third layer over the second layer made of the second metal, and a fourth layer over the third layer made of the first metal;

forming a third dielectric layer over the magnetic core and the second dielectric layer;
forming vias extending through the second dielectric layer and the third dielectric layer; and
after forming the vias, forming an upper coil segment over the third dielectric layer and the magnetic core, wherein the vias connect the upper coil segment with the lower coil segment.

2. The method of claim 1 , wherein the anisotropically etching a top portion of the second dielectric layer stops before reaching the lower coil segment and creates an opening with a substantially rectangular cross-section.

3. The method of claim 2 , wherein the anisotropically etching a top portion of the second dielectric layer is performed by a plasma etch process.

4. The method of claim 1 , wherein the second dielectric layer is formed using a material selected from the group consisting essentially of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof.

5. The method of claim 1 , wherein the first layer of the film structure has a thickness of about 50 Å, the second layer of the film structure has a thickness of about 150 Å, the third layer of the film structure has a thickness of about 2000 Å, and the fourth layer of the film structure has a thickness of about 50 Å.

6. The method of claim 1 , further comprising after the depositing magnetic material in the opening, removing excess magnetic material outside the opening by a planarization process.

7. The method of claim 1 , wherein the third dielectric layer is formed using a material selected from the group consisting essentially of polybenzoxazole (PBO), polyimide, benzocyclobutene, and combinations thereof.

8. The method of claim 1 , wherein the vias are formed adjacent to and along opposing sidewalls of the magnetic core.

9. The method of claim 1 , further comprising forming at least one dielectric layer over the upper coil segment.

10. A method of forming an integrated inductor in a semiconductor device, comprising:
forming a lower coil segment in a first passivation layer disposed over a substrate;
creating an opening in a second passivation layer disposed over the first passivation layer, wherein the second passivation layer extends continuously without an interface from a first side of the second passivation layer contacting the first passivation layer to a second side of the second passivation layer opposing the first side, wherein the opening overlies the lower coil segment and has straight sidewalls and a flat bottom surface, with the flat bottom surface disposed between the first side and the second side of the second passivation layer, and wherein the flat bottom surface of the opening, the first side of the second passivation layer, and the second side of the second passivation layer are parallel to a major surface of the substrate;
filling the opening with magnetic material to form a magnetic core, wherein the filling the opening comprises successively forming a plurality of film structures in the opening, wherein each of the plurality of film structures comprise a first film comprising a first metal, a second film comprising the first metal, a third film comprising a second metal, and a fourth film comprising an oxide of the second metal, and wherein the third film and the fourth film are between the first film and the second film;
forming an upper coil segment over the magnetic core; and
forming vias connecting the upper coil segment and the lower coil segment.

11. The method of claim 10 , wherein the opening is created by an anisotropic plasma etch process, wherein the anisotropic plasma etch process removes a top portion of the second passivation layer without exposing the lower coil segment in the first passivation layer.

12. The method of claim 10 , wherein the filling the opening with magnetic material is performed by repeating a deposition process multiple cycles, wherein a first deposition cycle forms a first film structure in the opening, wherein each additional deposition cycle forms a new film structure over an earlier formed film structure in the opening.

13. The method of claim 12 , wherein the deposition process is repeated about 22 cycles, and wherein the film structure formed in each deposition cycle comprise a layer of Ta with a thickness of about 50 Å, a layer of CoZrTa with a thickness of about 2000 Å, a layer of an oxide of CoZrTa with a thickness of about 150 Å, and another layer of Ta with a thickness of about 50 Å.

14. The method of claim 10 , further comprising forming a third passivation layer over the magnetic core and the second passivation layer, before forming the upper coil segment.

15. The method of claim 14 , wherein the forming vias connecting the upper coil segment and lower coil segment is performed before the forming an upper coil segment, and wherein the vias are formed in the third passivation layer and the second passivation layer along opposing sidewalls of the magnetic core.

16. A semiconductor device, comprising:
a first dielectric layer over a substrate;
a lower coil segment in the first dielectric layer;
an upper coil segment over the lower coil segment;
a magnetic core disposed between and insulated from the lower coil segment and the upper coil segment, wherein the magnetic core has a substantially rectangular cross-section and is formed in a second dielectric layer disposed over the first dielectric layer and under the upper coil segment, wherein an upper surface of the magnetic core is coplanar with an upper surface of the second dielectric layer, wherein the magnetic core has a thickness smaller than a thickness of the second dielectric layer, wherein the magnetic core comprises repeated layers of a film structure, and wherein the film structure comprises a first film comprising a first metal, a second film comprising the first metal, a third film comprising a second metal and a fourth film comprising an oxide of the second metal, with the third film and the fourth film being disposed between the first film and the second film;
a third dielectric layer disposed over the magnetic core and the second dielectric layer and below the upper coil segment; and
a plurality of vias disposed along opposing sidewalls of the magnetic core, wherein the vias extend through the second dielectric layer and the third dielectric layer to connect the upper coil segment with the lower coil segment.

17. The semiconductor device of claim 16 , wherein the second dielectric layer comprises a material selected from the group consisting essentially of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof.

18. The semiconductor device of claim 16 , wherein the third dielectric layer compri

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Chun-Tsung
• Lu Jiech-Fun
• Su Yen-Shuo

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W44/501 Primary

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H01L28/10 Primary

  Electricity · mapped topic