Patterned memory-network data transfer

US12216575B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12216575-B2
Application numberUS-202217858104-A
CountryUS
Kind codeB2
Filing dateJul 6, 2022
Priority dateJul 6, 2022
Publication dateFeb 4, 2025
Grant dateFeb 4, 2025

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A network device includes a first interface, a second interface, and circuitry. The first interface is configured to communicate at least with a memory. The second interface is configured to communicate over a network with a peer network device. The circuitry is configured to receive a request to transfer data over the network between the memory and the peer network device in accordance with (i) a pattern of offsets to be accessed in the memory and (ii) a memory key representing a memory space to be accessed using the pattern, and to transfer the data in accordance with the request.

First claim

Opening claim text (preview).

The invention claimed is: 1. A network device, comprising: a first interface, configured to communicate at least with a memory; a second interface, configured to communicate over a network with a peer network device; and circuitry, configured to pre-register a plurality of patterns of offsets, to pre-associate a memory key representing a memory space to be accessed with a given pattern from the plurality of patterns of offsets, to receive a request to transfer data over the network between the memory and the peer network device, wherein the request indicates the memory key, but not the given pattern pre-associated with the memory key, and to transfer the data in accordance with the request using the memory key and the given pattern pre-associated with the memory key. 2. The network device according to claim 1 , wherein the circuitry is configured to receive the request as a work-request via the first interface. 3. The network device according to claim 1 , wherein each of the pre-registered patterns of offsets comprises one of (i) a pattern that accesses a contiguous memory space, (ii) a pattern that accesses a non-contiguous memory space, and (iii) a strided pattern. 4. The network device according to claim 1 , wherein the request specifies multiple memory keys representing respective memory spaces to be accessed using the pattern. 5. The network device according to claim 1 , wherein the memory space represented by the memory key is one of a virtual memory space and a physical memory space. 6. The network device according to claim 1 , wherein, in response to receiving a re-association instruction, the circuitry is configured to associate the memory key with a different pattern. 7. The network device according to claim 1 , wherein the pattern is pre-associated in the network device with at least one additional memory key. 8. The network device according to claim 1 , wherein the request specifies a starting virtual address or initial offset parameter for the pattern. 9. The network device according to claim 1 , wherein the pattern specifies the offsets using a nested representation that comprises at least one internal pattern. 10. The network device according to claim 1 , wherein the pattern specifies the offsets using an iterative representation that defines (i) a basic pattern to be iterated multiple times, (ii) a number of times the basic pattern is to be iterated, and (iii) an offset between successive iterations of the basic pattern. 11. The network device according to claim 1 , wherein the request is associated with a scatter or gather command. 12. The network device according to claim 1 , wherein the request is associated with an InfiniBand transaction. 13. The network device according to claim 1 , wherein the request is associated with an Ethernet transaction. 14. A method for data transfer, comprising: in a network device, communicating with a memory and, over a network, with a peer network device; pre-registering, in the network device, a plurality of patterns of offsets; pre-associating a memory key representing a memory space to be accessed with a given pattern from the plurality of patterns of offsets; receiving in the network device a request to transfer data over the network between the memory and the peer network device, wherein the request indicates the memory key, but not the given pattern pre-associated with the memory key; and transferring the data in accordance with the request using the memory key and the given pattern pre-associated with the memory key. 15. The method according to claim 14 , wherein receiving the request comprises receiving the request as a work-request via the first interface. 16. The method according to claim 14 , wherein each of the multiple pre-registered patterns of offsets comprises one of (i) a pattern that accesses a contiguous memory space, (ii) a pattern that accesses a non-contiguous memory space, and (iii) a strided pattern. 17. The method according to claim 14 , wherein the request specifies multiple memory keys representing respective memory spaces to be accessed using the pattern. 18. The method according to claim 14 , wherein the memory space represented by the memory key is one of a virtual memory space and a physical memory space. 19. The method according to claim 14 , and comprising, in response to receiving a re-association instruction, associating the memory key with a different pattern. 20. The method according to claim 14 , wherein the pattern is pre-associated in the network device with at least one additional memory key. 21. The method according to claim 14 , wherein the request specifies a starting virtual address or initial offset parameter for the pattern. 22. The method according to claim 14 , wherein the pattern specifies the offsets using a nested representation that comprises at least one internal pattern. 23. The method according to claim 14 , wherein the pattern specifies the offsets using an iterative representation that defines (i) a basic pattern to be iterated multiple times, (ii) a number of times the basic pattern is to be iterated, and (iii) an offset between successive iterations of the basic pattern. 24. The method according to claim 14 , wherein the request is associated with a scatter or gather command. 25. The method according to claim 14 , wherein the request is associated with an InfiniBand transaction. 26. The method according to claim 14 , wherein the request is associated with an Ethernet transaction.

Assignees

Inventors

Classifications

  • for main memory peripheral accesses (e.g. I/O or DMA) · CPC title

  • Distributed shared memory [DSM], e.g. remote direct memory access [RDMA] · CPC title

  • using bus bridges (G06F13/4022 takes precedence) · CPC title

  • Setup of application sessions (admission control or resource allocation in data switching networks H04L47/70) · CPC title

  • with address mapping · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12216575B2 cover?
A network device includes a first interface, a second interface, and circuitry. The first interface is configured to communicate at least with a memory. The second interface is configured to communicate over a network with a peer network device. The circuitry is configured to receive a request to transfer data over the network between the memory and the peer network device in accordance with (i…
Who is the assignee on this patent?
Mellanox Technologies Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/4027. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 04 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).