Near-memory data reorganization engine

Patent metadata

Field	Value
Publication number	US-2017242590-A1
Application number	US-201615047173-A
Country	US
Kind code	A1
Filing date	Feb 18, 2016
Priority date	Feb 18, 2016
Publication date	Aug 24, 2017
Grant date	—

Abstract

A memory subsystem package is provided that has processing logic for data reorganization within the memory subsystem package. The processing logic is adapted to reorganize data stored within the memory subsystem package. In some embodiments, the memory subsystem package includes memory units, a memory interconnect, and a data reorganization engine (“DRE”). The data reorganization engine includes a stream interconnect and DRE units including a control processor and a load-store unit. The control processor is adapted to execute instructions to control a data reorganization. The load-store unit is adapted to process data move commands received from the control processor via the stream interconnect for loading data from a load memory address of a memory unit and storing data to a store memory address of a memory unit.

First claim

1 . A memory subsystem package having processing logic for data reorganization within the memory subsystem package, the memory subsystem package comprising:
a plurality of memory units having memory; a memory interconnect connecting memory units to data reorganization engine units and enabling data reorganization engine units to access memory of the memory units; and a data reorganization engine comprising:
a stream interconnect connecting data reorganization engine units of the data reorganization engine and enabling the data reorganization engine units to transmit data and receive data via the stream interconnect;
a control processor that is a data reorganization engine unit, that is connected to the memory interconnect, and that is connected to the stream interconnect, the control processor adapted to execute instructions to perform a data reorganization; and
a load-store unit that is a data reorganization engine unit, that is connected to the memory interconnect, that is connected to the stream interconnect, and that is adapted to process data move commands received from the control processor via the stream interconnect for loading data from a load memory address of a memory unit and for storing data to a store memory address of a memory unit.

2 . The memory subsystem package of claim 1 wherein the load-store unit comprises:
a load component adapted to load data from a load memory address and output the loaded data onto the stream interconnect;
a store component adapted to input data from the stream interconnect and store the input data to a store memory address; and
a sequencer component adapted to input via the stream interconnect commands sent by the control processor for controlling data reorganization of data stored in a memory unit and to effect the data reorganization by supplying load memory addresses to the load component and store memory addresses to the store component.

3 . The memory subsystem package of claim 2 wherein the load-store unit further comprises:
a load FIFO buffer that is connected to a load module of the load component and the sequencer component and that is adapted to buffer load memory addresses supplied by the sequencer component to the load component; and
a store FIFO buffer that is connected to a store module of the store component and the sequencer component and that is adapted to buffer store memory addresses supplied by the sequencer component to the store component.

4 . The memory subsystem package of claim 2 wherein the sequencer component includes a data address register adapted to store a data memory address and a view memory address register adapted to store a view memory address, a data memory address being a memory address of a data buffer of a memory unit to be reorganized into a view buffer of a memory unit and a view memory address being a memory address of the view buffer.

5 . The memory subsystem package of claim 4 wherein the sequencer component is adapted to, when reorganizing the data of the data buffer into the view buffer:
prior to each load of data, calculate a data buffer offset based on a command provided by the control processor and supply to the load component a sum of the data buffer memory address and the data buffer offset as the load memory address;
initialize a store memory address to the view memory address; and
prior to each store of data, supply to the store component the store memory address, and after supplying the store memory address, increment the store memory address.

6 . The memory subsystem package of claim 4 wherein the sequencer component is adapted to, when reorganizing the data of the view buffer into the data buffer:
prior to each store of data, calculate a data buffer offset based on a command provided by the control processor and supply to the store component a sum of the data buffer memory address and the data buffer offset as the store memory address;
initialize a load memory address to the view memory address; and
prior to each load of data, supply to the load component the load memory address, and after supplying the load memory address, increment the load memory address.

7 . The memory subsystem package of claim 1 wherein the load-store unit is adapted to receive from the control processor via the stream interconnect a stream of data buffer offsets and use the data buffer offsets when performing a scatter/gather data reorganization.

8 . The memory subsystem package of claim 1 wherein the load-store unit is adapted to receive from the control processor via the stream interconnect an element size and a stride for a strided data reorganization.

9 . The memory subsystem package of claim 1 wherein the data reorganization engine includes multiple load-store unit units.

10 . The memory subsystem package of claim 9 wherein the data reorganization engine includes multiple control processors.

11 . The memory subsystem package of claim 1 wherein the data reorganization engine includes a host control interface that is a data reorganization engine unit, that is connected to the memory interconnect and the stream interconnect, and that is adapted to provide to a host processor access to the data reorganization engine.

12 . The memory subsystem package of claim 1 wherein the data reorganization engine includes an operation component that is connected to the stream interconnect and that is adapted to input data via the stream interconnect, perform an operation on the data to generate result data, and to output the result data via the stream interconnect.

13 . The memory subsystem package of claim 12 wherein the data reorganization engine includes multiple operation components.

14 . The memory subsystem package of claim 1 wherein the control processor includes a memory adapted to store instructions executable by the control processor to control data reorganization.

15 . The memory subsystem package of claim 14 wherein the control processor is adapted to receive from a host processor instructions executable by the control processor.

16 . The memory subsystem package of claim 1 wherein the data reorganization engine includes a memory management unit to translate virtual addresses to physical addresses.

17 . A method performed by a host processor for reorganizing data of a data buffer into a view buffer, the data buffer and the view buffer being memory within a memory subsystem, the method comprising:
issuing a setup command to a data reorganization engine of the memory subsystem, the setup command specifying a data buffer memory address of the data buffer and setup parameters for reorganizing data of the data buffer; and issuing a fill command to the data reorganization engine of the memory subsystem, the fill command specifying fill parameters for reorganizing data of the data buffer into the view buffer, wherein upon completion of the fill command by the data reorganization engine, the view buffer contains the reorganized data of the data buffer.

18 . The method of claim 17 further comprising, after completion of the fill command, accessing data of the view buffer.

19 . The method of claim 18 further comprising, after accessing the data of the view buffer, issuing a drain command to the data reorganization engine of the memory subsystem, the drain command specifying drain parameters for reorganizing data of the view buffer into the data buffer.

20 . The method of claim 17 wherein the reorganizing is scatter/gather reorganizing, the setup parameters include a data buffer memory address an

Assignees

• L Livermore Nat Security Llc

Inventors

• Gokhale Maya
• Lloyd G Scott

Classifications

• G06F12/0223

  User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

• G06F2212/1048

  Scalability · CPC title

• G06F15/785

  with decentralized control, e.g. smart memories · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F2212/1056

  Simplification · CPC title