Imaging device and electronic device

Patent metadata

Field	Value
Publication number	US-12212873-B2
Application number	US-202118024084-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Sep 25, 2020
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

The present invention relates to a highly functional imaging device that can be manufactured through a small number of steps. The imaging device is formed in such a manner that a first stacked body in which a plurality of devices are stacked and a second stacked body in which a plurality of devices are stacked are bonded to each other. For example, a pixel circuit, a driver circuit of a pixel, and the like can be provided in the first stacked body, and a reading circuit of the pixel circuit, a memory circuit, a driver circuit of the memory circuit, and the like can be provided in the second stacked body. With these structures, the imaging device which is small can be formed. Furthermore, wiring delay or the like can be prevented by stacking circuits, so that high-speed operation can be performed.

First claim

The invention claimed is:

1. An imaging device comprising:
a first layer comprising a reading circuit over a substrate;
a second layer over the first layer, the second layer comprising:
a memory circuit;
a first insulating layer over the memory circuit; and
a first conductive layer embedded in the first insulating layer;

a third layer over the second layer, the third layer comprising:
a second insulating layer in contact with the first insulating layer;
a second conductive layer embedded in the second insulating layer; and
a pixel circuit over the second conductive layer; and

a fourth layer comprising a photoelectric conversion device over the third layer,
wherein the photoelectric conversion device is electrically connected to the pixel circuit,
wherein the memory circuit is electrically connected to the reading circuit,
wherein the first conductive layer is electrically connected to the reading circuit,
wherein the second conductive layer is electrically connected to the pixel circuit,
wherein the first conductive layer and the second conductive layer are directly bonded to each other,
wherein the memory circuit comprises a memory cell, and
wherein the memory cell comprises a capacitor including a ferroelectric layer.

2. The imaging device according to claim 1 ,
wherein the pixel circuit and the memory circuit each comprise a transistor including a metal oxide in a channel formation region,
wherein the reading circuit comprises a transistor including silicon in a channel formation region, and
wherein the photoelectric conversion device is a photodiode including silicon in a photoelectric conversion layer.

3. The imaging device according to claim 2 ,
wherein the metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

4. The imaging device according to claim 1 ,
wherein the pixel circuit, the memory circuit, and the reading circuit each comprise a transistor including silicon in a channel formation region, and
wherein the photoelectric conversion device is a photodiode including silicon in a photoelectric conversion layer.

5. The imaging device according to claim 1 ,
wherein the first conductive layer and the second conductive layer are formed using the same metal material, and
wherein the first insulating layer and the second insulating layer are formed using the same insulating material.

6. The imaging device according to claim 1 ,
wherein the ferroelectric layer is a metal oxide including Hf and Zr.

7. An electronic device comprising the imaging device according to claim 1 , and a display device.

8. An imaging device comprising:
a first layer comprising a reading circuit over a substrate;
a second layer over the first layer, the second layer comprising:
a memory circuit;
a first insulating layer over the memory circuit; and
a first conductive layer embedded in the first insulating layer;

a third layer over the second layer, the third layer comprising:
a second insulating layer in contact with the first insulating layer;
a second conductive layer embedded in the second insulating layer; and
a pixel circuit over the second conductive layer; and

a fourth layer comprising a photoelectric conversion device over the third layer,
wherein the photoelectric conversion device is electrically connected to the pixel circuit,
wherein the memory circuit is electrically connected to the reading circuit,
wherein the first conductive layer is electrically connected to the reading circuit,
wherein the second conductive layer is electrically connected to the pixel circuit, and
wherein the first conductive layer and the second conductive layer are directly bonded to each other.

9. The imaging device according to claim 8 ,
wherein the pixel circuit and the memory circuit each comprise a transistor including a metal oxide in a channel formation region,
wherein the reading circuit comprises a transistor including silicon in a channel formation region, and
wherein the photoelectric conversion device is a photodiode including silicon in a photoelectric conversion layer.

10. The imaging device according to claim 9 ,
wherein the metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

Assignees

• Semiconductor Energy Lab

Inventors

• Negoro Yusuke
• Shishido Hideaki

Classifications

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/803 Primary

  Pixels having integrated switching, control, storage or amplification elements · CPC title

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10B53/30

  characterised by the memory core region · CPC title