Light receiving elements for photoelectric conversion and capacitor elements for charge storing in joined substrates

Patent metadata

Field	Value
Publication number	US-9293496-B2
Application number	US-201414464423-A
Country	US
Kind code	B2
Filing date	Aug 20, 2014
Priority date	Aug 21, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Provided are a semiconductor device in which a solid-state image sensing element having a backside-illuminated structure and capacitor elements storing therein some of the charges supplied from light receiving elements has further improved reliability and a manufacturing method thereof. In the solid-state image sensing element of the semiconductor device, first and second substrates are joined together at a junction surface. The first substrate is formed with photodiodes. The second substrate is formed with the capacitor elements. The photodiodes and the capacitor elements are placed to be opposed to each other. In the first substrate, first coupling portions for coupling to the second substrate are placed. In the second substrate, second coupling portions for coupling to the first substrate are placed. A first gap portion between the first coupling portions and a second gap portion between the second coupling portions are placed to overlap a first light blocking film.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first substrate forming at least a part of each of a plurality of pixels including a plurality of light receiving elements in each of which photoelectric conversion is performed; and
a second substrate having capacitor elements which store therein charges supplied from the light receiving elements,
wherein the first substrate and the second substrate are joined together at a junction surface therebetween so as to be integrated with each other,
wherein the light receiving elements and the capacitor elements are placed so as to be opposed to each other in a direction perpendicular to the junction surface,
wherein the capacitor elements are at positions away from a surface of the second substrate corresponding to the junction surface,
wherein the first substrate includes:
a light-receiving-element-side light blocking film placed on a side of each of the light receiving elements where light is supplied to the light receiving element so as to block the light supplied to the light receiving element; and
a plurality of first coupling portions formed at a surface of the first substrate corresponding to the junction surface so as to electrically couple the first substrate and the second substrate to each other,
wherein the second substrate includes:
a plurality of second coupling portions formed at the surface of the second substrate corresponding to the junction surface so as to be electrically coupled to the first coupling portions, and
wherein a first gap portion interposed between the first coupling portions and a second gap portion interposed between the second coupling portions, each of which is present outside regions overlapping the light receiving elements in planar view, are placed so as to overlap the light-receiving-element-side light blocking film in the direction perpendicular to the junction surface at which the first substrate and the second substrate are joined together.

2. A semiconductor device according to claim 1 , further comprising:
a capacitor-element-side light blocking film which is provided so as to overlap the light receiving elements in the direction perpendicular to the junction surface and block light traveling from the light receiving elements toward the second substrate,
wherein the capacitor-element-side light blocking film is located between the light receiving elements and the capacitor elements in the direction perpendicular to the junction surface.

3. A semiconductor device according to claim 2 ,
wherein the capacitor-element-side light blocking film is formed so as to completely overlap the light receiving elements in the direction perpendicular to the junction surface.

4. A semiconductor device according to claim 1 ,
wherein the pixels are arranged in a grid pattern in planar view, and
wherein the first coupling portions and the second coupling portions are arranged such that a direction of a vector of a shortest length of the first gap portion between the pair of first coupling portions adjacent to each other in planar view and a direction of a vector of a shortest length of the second gap portion between the pair of second coupling portions adjacent to each other in planar view extend obliquely to directions in which the pixels are aligned.

5. A semiconductor device according to claim 2 ,
wherein the capacitor-element-side light blocking film is placed in the first substrate.

6. A semiconductor device according to claim 5 ,
wherein the first substrate includes:
a first interlayer insulating film; and
a plurality of first interconnect layers stacked such that the first interlayer insulating film is interposed therebetween, and
wherein a part of the one of the first interconnect layers which is closest to the light receiving elements is used as the capacitor-element-side light blocking film.

7. A semiconductor device according to claim 2 ,
wherein the capacitor-element-side light blocking film is placed in the second substrate.

8. A semiconductor device according to claim 1 ,
wherein each of the capacitor elements includes:
a first electrode as a semiconductor region in a supporting substrate forming the second substrate in which a conductive impurity is diffused;
a dielectric layer covering at least a part of an upper surface of the first electrode; and
a second electrode as a metal layer or a semiconductor layer containing a conductive impurity which covers at least a part of an upper surface of the dielectric layer.

9. A semiconductor device according to claim 1 ,
wherein each of the capacitor elements includes:
a first electrode as a semiconductor layer containing a conductive impurity;
a dielectric layer covering at least a part of an upper surface of the first electrode; and
a second electrode as a semiconductor layer containing a conductive impurity or a metal layer which covers at least a part of an upper surface of the dielectric layer.

10. A semiconductor device according to claim 1 ,
wherein each of the capacitor elements includes:
a first electrode as a metal layer;
a dielectric layer covering at least a part of an upper surface of the first electrode; and
a second electrode as a metal layer covering at least a part of an upper surface of the dielectric layer.

11. A semiconductor device according to claim 1 ,
wherein the second substrate includes:
a second interlayer insulating film; and
a plurality of second interconnect layers formed such that the second interlayer insulating film is interposed therebetween,
wherein a portion including a first electrode as one of the stacked second interconnect layers, a dielectric layer as the second interlayer insulating film which covers at least a part of an upper surface of the first electrode, and a second electrode as another of the second interconnect layers which is other than the one of the second interconnect layers and covers at least a part of an upper surface of the dielectric layer is used as each of the capacitor elements.

Assignees

• Renesas Electronics Corp

Inventors

• Kashihara Keiichiro

Classifications

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10F39/8063

  Microlenses · CPC title

• H10F39/8053

  Colour filters · CPC title

• H10F39/024

  of coatings or optical elements · CPC title

• H10F39/8057

  Optical shielding · CPC title