Power supply circuit

Patent metadata

Field	Value
Publication number	US-12212866-B2
Application number	US-202318500449-A
Country	US
Kind code	B2
Filing date	Nov 2, 2023
Priority date	Nov 5, 2021
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.

First claim

What is claimed is:

1. A power supply circuit comprising:
a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance;
a second transistor device comprising a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance, wherein the second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop;
a capacitor having a first terminal coupled to the second gate and the fourth gate, and a second terminal coupled to a common reference node; and
a circuit element connected between a reference voltage node and the first terminal of the capacitor and configured to couple a voltage of the reference node to the first terminal of the capacitor.

2. The circuit according to claim 1 , wherein:
the closed regulation loop comprises an operational amplifier having a non-inverting input configured to receive a voltage to be followed, and an inverting input configured to receive a voltage present on a source of the first transistor device; and
the first and the third gates are coupled to an output of the operational amplifier.

3. The circuit according to claim 1 , wherein the first gate of the first transistor device and the third gate of the second transistor device are back gates.

4. The circuit according to claim 1 , wherein the voltage of the reference voltage node is generated by a further closed regulation loop comprising a transistor having a front gate coupled to an output of an operational amplifier; and
transistors of the first and second transistor devices and the transistor of the further closed regulation loop are matched together.

5. The circuit according to claim 1 , wherein:
the closed regulation loop comprises a first operational amplifier having a non-inverting input configured to receive a voltage to be followed, and an inverting input configured to receive a voltage present on a source of the first transistor device; and
the first and the third gates are coupled to an output of the first operational amplifier;
the first gate of the first transistor device and the third gate of the second transistor device are back gates;
the voltage of the reference voltage node is generated by a further closed regulation loop comprising a transistor having a front gate coupled to an output of a second operational amplifier;
transistors of the first and second transistor devices and the transistor of the further closed regulation loop are matched together;
the transistor of the further closed regulation loop comprises a back gate; and
a voltage applied to the first gate of the first transistor device by the first operational amplifier is configured to be substantially equal to a voltage applied to said back gate of the transistor of the further closed regulation loop.

6. The circuit according to claim 1 , wherein:
the first transistor device comprises a first transistor comprising the first gate and a second transistor comprising the second gate, a source of the first transistor being connected to a source of the second transistor, and a drain of the first transistor being connected to a drain of the second transistor; and
the second transistor device comprises a third transistor comprising the third gate and a fourth transistor comprising the fourth gate, a source of the third transistor being connected to a source of the fourth transistor, and a drain of the third transistor being connected to a drain of the fourth transistor.

7. The circuit according to claim 6 , wherein a width of the second transistor is greater than a width of the first transistor or a width of the third transistor is greater than a width of the fourth transistor.

8. The circuit according to claim 1 , further comprising a plurality of second transistor devices having third gates coupled together, wherein each second transistor device of the plurality of second transistor devices are configured to power a different load.

9. The circuit according to claim 8 , wherein sources of each second transistor device of the plurality of second transistor devices are coupled together.

10. An image sensor comprising:
the power supply circuit according to claim 8 ; and
a plurality of pixel columns, each pixel column of the plurality of pixel columns powered by a corresponding second transistor device of the plurality of second transistor devices.

11. The circuit according to claim 1 , wherein a width of the second transistor device is a multiple k of a width of the first transistor device, wherein multiple k is equal to or greater than 5.

12. The circuit according to claim 1 , wherein the first transistor device comprises a first main conducting node configured to supply the closed regulation loop.

13. The circuit according to claim 12 , wherein a first main conducting node of the second transistor device is configured to supply the at least one load, and the first main conducting node of the first transistor device is configured to have a capacitance that is smaller than a capacitance of the first main conducting node of the second transistor device.

14. The circuit according to claim 13 , wherein the first main conducting node of the first transistor device is not connected to the second transistor device.

15. The circuit according to claim 14 , wherein a width of the second transistor device is a multiple k of a width of the first transistor device, the multiple k being equal to or greater than 1, and wherein the first main conducting node of the first transistor device is configured to have a capacitance that is 10*k times smaller than a capacitance of the load.

16. An image sensor comprising:
the power supply circuit according to claim 1 ; and
at least one pixel coupled to the power supply circuit.

17. The circuit according to claim 1 , wherein the circuit element comprises a sampling switch.

18. A load powering method, comprising:
controlling a first gate of a first transistor device with a closed regulation loop;
controlling a second gate of the first transistor device with a reference voltage, the first gate being associated with a first transconductance and the second gate being associated with a transconductance greater than that associated with the first gate;
controlling a third gate of a second transistor device with the closed regulation loop;
controlling a fourth gate of the second transistor device with the reference voltage, the third gate being associated with a second transconductance and the fourth gate being associated with a transconductance greater than the second transconductance; and
providing power to at least one load via the second transistor device.

19. The method of claim 18 , wherein the first gate of the first transistor device and the third gate of the second transistor device are back gates.

20. The method of claim 18 , wherein:
the first transistor device comprises a first transistor comprising the first gate and a second transistor comprising the second gate, a source of the first transistor being connected to a source of the second transistor, and a drain of the first transistor being connected to a drain of the second transistor; and
the second transistor device comprises a third transistor comprising the third gate and a fourth transistor comprising the fourth gate, a source of the third transistor being connected

Assignees

• St Microelectronics Grenoble 2

Inventors

• Simony Laurent

Classifications

• H02M3/155

  using semiconductor devices only · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H04N25/709 Primary

  Circuitry for control of the power supply · CPC title