Method, apparatus and system for back gate biasing for FD-SOI devices

Patent metadata

Field	Value
Publication number	US-9923527-B2
Application number	US-201615148668-A
Country	US
Kind code	B2
Filing date	May 6, 2016
Priority date	May 6, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

At least one method, apparatus and system disclosed involves providing semiconductor device having transistors comprising back gates and front gates. The semiconductor device comprises a signal processing unit for processing an input signal to provide an output signal. The signal processing unit includes a first transistor and a second transistor. The first transistor includes a first back gate electrically coupled to a first front gate. The signal processing unit also includes a second transistor operatively coupled to the first transistor. The second transistor includes a second back gate electrically coupled to a second front gate. The semiconductor device also includes a gain circuit for providing a gain upon the output signal. The semiconductor device also includes a bias circuit to provide a first bias signal to the first back gate and a second bias signal to the second back gate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a signal processing unit for processing an input signal to provide an output signal, said signal processing unit comprising:
a first transistor and a second transistor, wherein said first transistor comprises a first back gate and a first front gate; and
said second transistor is operatively coupled to said first transistor, wherein said second transistor comprises a second back gate and a second front gate;

a gain circuit for providing a gain upon said output signal; and
a bias circuit to provide a first bias signal to said first back gate and a second bias signal to said second back gate, wherein said bias circuit comprises:
a voltage divider circuit to provide a divided voltage signal;
a current mirror for providing a current-proportional voltage signal based on said divided voltage signal;
a first amplifier circuit configured to receive said current-proportional voltage signal and a current-reference voltage signal and provide said second bias signal; and
a second amplifier circuit configured to receive said divided voltage signal and said output signal and provide said first bias signal.

2. The semiconductor device of claim 1 , wherein said first transistor is a PMOS device and said second transistor is an NMOS device.

3. The semiconductor device of claim 2 , wherein said first bias signal is a positive signal voltage signal and said second bias signal is a negative voltage signal.

4. The semiconductor device of claim 1 , wherein said gain circuit is adapted to provide at least one of a unity gain and an amplification of said output signal.

5. The semiconductor device of claim 1 , wherein said input signal is a radio-frequency signal.

6. The semiconductor device of claim 1 , wherein the drain of said first transistor is electrically coupled to the drain of said second transistor, wherein an output signal node is coupled to said drain of said first transistor.

7. The semiconductor device of claim 1 , wherein said second amplifier circuit comprises:
an RC circuit at a first input, wherein said divided voltage signal is provided to said first input; and
a second input, wherein said output signal is provided to said second input; and
wherein the gain bandwidths of said first and second amplifier circuits are limited to below the radio frequency (RF) passband.

8. The semiconductor device of claim 1 , wherein said current mirror comprises a current to voltage converter configured for converting a current signal into said current-proportional voltage signal.

9. The semiconductor device of claim 1 , wherein said first and second transistors are at least one of an FD SOI transistor, wherein said FD SOI transistor is at least one of an FD SOI LVT transistor, an FD SOI SLVT transistor, an FD SOI RVT transistor, or an FD SOI HVT transistor.

10. A system, comprising:
a semiconductor device processing system to process a semiconductor wafer for manufacturing a semiconductor device, wherein semiconductor device processing system comprising:
a design unit configured to provide parameter for manufacturing said semiconductor device comprising:
a signal processing unit for processing an input signal to provide an output signal, said signal processing unit comprising:
a first transistor and a second transistor, wherein said first transistor comprises a first back gate and a first front gate; and
said second transistor is operatively coupled to said first transistor, wherein said second transistor comprises a second back gate and a second front gate;

a gain circuit for providing a gain upon said output signal; and
a bias circuit to provide a first bias signal to said first back gate and a second bias signal to said second back gate, wherein said bias circuit comprises a voltage divider circuit to provide a divided voltage signal; a current mirror for providing a current-proportional voltage signal based on said divided voltage signal; a first amplifier circuit configured to receive said current-proportional voltage signal and a current-reference voltage signal and provide said second bias signal; and a second amplifier circuit configured to receive said divided voltage signal and said output signal and provide said first bias signal;
and

a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system for manufacturing said semiconductor device.

11. The system of claim 10 , wherein said second amplifier circuit comprises:
an RC circuit at a first input, wherein said divided voltage signal is provided to said first input; and
a second input, wherein said output signal is provided to said second input; and
wherein said unity gain band widths of said first and second amplifier circuits are larger than the frequency of said input signal.

Assignees

• Globalfoundries Inc

Inventors

• Mckay Thomas G

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P72/04

  Apparatus for manufacture or treatment · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• G06F30/30

  Circuit design · CPC title