Electronic component comprising first and second conductive traces and a void formed in an insulative layer between the first and second traces providing crosstalk reduction

Patent metadata

Field	Value
Publication number	US-12207392-B2
Application number	US-202217933693-A
Country	US
Kind code	B2
Filing date	Sep 20, 2022
Priority date	Sep 20, 2022
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

An electronic component includes a first trace configured to transmit a first signal and a second trace configured to transmit a second signal. The electronic component further includes a layer of conductive material separated from the first and second traces by a layer of insulative material. The electronic component further includes a first vertical wall formed in direct contact with the layer of conductive material. The electronic component further includes a second vertical wall formed in direct contact with the layer of conductive material. The second vertical wall is separated from the first vertical wall by a void, and the void extends between the first trace and the second trace.

First claim

What is claimed is:

1. An electronic component, comprising:
a first trace configured to transmit a first signal;
a second trace configured to transmit a second signal;
a layer of conductive material separated from the first and second traces by a layer of insulative material;
a first vertical wall formed in direct contact with and perpendicular to the layer of conductive material; and
a second vertical wall formed in direct contact with and perpendicular to the layer of conductive material, wherein:
the second vertical wall is separated from the first vertical wall by a void, and the void extends between the first trace and the second trace.

2. The electronic component of claim 1 , wherein:
an uppermost surface of the layer of conductive material is exposed by the void.

3. The electronic component of claim 1 , wherein:
the layer of conductive material provides an electrical ground.

4. The electronic component of claim 1 , wherein:
the first vertical wall is formed in direct contact with the layer of insulative material; and
the second vertical wall is formed in direct contact with the layer of insulative material.

5. The electronic component of claim 1 , wherein:
the first trace is in direct contact with the layer of insulative material; and
the second trace is in direct contact with the layer of insulative material.

6. The electronic component of claim 5 , wherein:
the first trace is separated from the first vertical wall by the layer of insulative material; and
the second trace is separated from the second vertical wall by the layer of insulative material.

7. The electronic component of claim 1 , further comprising:
a layer of dielectric material covering the first trace, the second trace, and an uppermost surface of the layer of insulative material.

8. The electronic component of claim 1 , wherein:
the first and second vertical walls are made of a further conductive material; and
the further conductive material is the same conductive material as the layer of conductive material.

9. An electronic component, comprising:
a first insulative layer arranged in direct contact with a first conductive layer;
a first trace configured to transmit a first signal and a second trace configured to transmit a second signal, the first and second traces separated from the first conductive layer by the first insulative layer;
first and second vertical walls extending from a surface of the first conductive layer and in direct contact with the first insulative layer, the first and second vertical walls separated from one another by a first void;
a second insulative layer separated from the first insulated layer and from the first and second traces by a dielectric layer;
a second conductive layer in direct contact with the second insulative layer; and
third and fourth vertical walls extending from a surface of the second conductive layer and in direct contact with the second insulative layer, the third and fourth vertical walls separated from one another by a second void.

10. The electronic component of claim 9 , wherein:
the third vertical wall is arranged directly above the first vertical wall and is separated from the first vertical wall; and
the fourth vertical wall is arranged directly above the second vertical and is separated from the second vertical wall.

11. The electronic component of claim 9 , wherein:
the first and second voids are continuous with one another.

12. The electronic component of claim 9 , wherein:
at least one of the first or second conductive layers provides an electrical ground.

13. The electronic component of claim 9 , wherein:
the first and second vertical walls are made of the same material as the first conductive layer; and
the third and fourth vertical walls are made of the same material as the second conductive layer.

14. The electronic component of claim 9 , wherein:
the first insulative layer and the second insulative layer are bonded together by the dielectric layer.

15. The electronic component of claim 9 , wherein:
the surface of the first conductive layer is exposed by the first void; and
the surface of the second conductive layer is exposed by the second void.

16. A method for making an electronic component, the method comprising:
forming a first trench and a second trench in a circuit board such that the first trench and the second trench are arranged between a first trace and a second trace of the circuit board;
partially filling each of the first and second trenches with conductive material to form a first vertical wall and a second vertical wall in direct contact with an uppermost surface of a conductive layer of the circuit board;
forming a first void between the first vertical wall and the second vertical wall so as to expose the uppermost surface the conductive layer between the first and second vertical walls.

17. The method of claim 16 , wherein:
forming the first and second trenches includes forming a first buffer between the first trench and the first trace and forming a second buffer between the second trench and the second trace.

18. The method of claim 16 , wherein:
forming the first and second trenches includes exposing the uppermost surface of the conductive layer of the circuit board.

19. The method of claim 16 , wherein:
forming the first and second trenches includes removing portions of an insulative layer of the circuit board and removing portions of a dielectric layer of the circuit board.

20. The method of claim 19 , wherein:
removing the portions of the insulative layer and the portions of the dielectric layer includes using a laser.

Assignees

• IBM

Inventors

• Doyle Matthew
• Long David Clifford
• Cocchini Matteo
• Budd Russell A
• Busby James
• Krabbenhoft Roger S
• Higby Arthur J

Classifications

• H01P3/081 Primary

  Microstriplines · CPC title

• H01P11/003

  Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines · CPC title

• H05K1/0219

  Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors · CPC title

• H05K1/024

  Dielectric details, e.g. changing the dielectric material around a transmission line · CPC title

• H05K3/4697

  having cavities, e.g. for mounting components (H05K3/4691 takes precedence) · CPC title