Thin film transistor, array substrate and display device having slanted gate electrodes

Patent metadata

Field	Value
Publication number	US-12206003-B2
Application number	US-202318093063-A
Country	US
Kind code	B2
Filing date	Jan 4, 2023
Priority date	Nov 20, 2019
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

A thin film transistor, an array substrate and a display device are provided. The thin film transistor is on a base substrate and includes a gate electrode, a first electrode, and a second electrode on the base substrate. The gate electrode includes a first body portion and a first extension portion extending along the first direction, electrically connected with the first body portion, and spaced apart from the first body portion by a first spacing. The first electrode includes a first overlapping end, an orthographic projection of the first overlapping end on the base substrate at least partially overlaps with an orthographic projection of the first body portion on the base substrate; a first compensation end at a side of the first overlapping end away from the first body portion, an orthographic projection of the first compensation end on the base substrate at least partially overlaps with an orthographic projection of the first extension portion on the base substrate; and a first intermediate portion connecting the first overlapping end and the first compensation end, an orthographic projection of the first intermediate portion on the base substrate is within an orthographic projection of the first spacing on the base substrate.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a plurality of first signal lines extending along a second direction and a plurality of second signal lines extending along a third direction on the base substrate, wherein the second direction and the third direction intersect with each other, and the plurality of first signal lines intersect with the plurality of second signal lines to define a plurality of light control units in an array; and
the plurality of light control units comprises a plurality of first light control units and a plurality of second light control units, the plurality of first light control units comprises a plurality of first thin film transistors, respectively; the plurality of second light control units comprises a plurality of second thin film transistors, respectively; the first thin film transistors included in the first light control units are axially symmetrical with the second thin film transistors included in the second light control units with respect to an axis of symmetry along the third direction, respectively; or, the first thin film transistors included in the first light control units after being displaced along the third direction are axially symmetrical with the second thin film transistors included in the second light control units with respect to an axis of symmetry parallel to the second signal line, respectively;
wherein each of the first thin film transistors and the second thin film transistors is provided on the base substrate and comprises a gate electrode, a first electrode, and a second electrode,
wherein the gate electrode comprises:
a first body portion extending along a first direction;
a first extension portion extending substantially along the first direction, the first extension portion is electrically connected with the first body portion and spaced apart from the first body portion by a first spacing; and
a first connection portion connecting the first body portion and the first extension portion;

wherein the first electrode extends along the first direction and comprises:
a first overlapping end;
a first compensation end at a side of the first overlapping end away from the first body portion; and
a first intermediate portion connecting the first overlapping end and the first compensation end;

wherein the first extension portion has a first end and a second end in the first direction, and the first body portion has a first end and a second end in the first direction;
the first connection portion connects the first end of the first extension portion with the first end of the first body portion;
the second end of the first extension portion and the second end of the first body portion are at a same side of the first connection portion; and
wherein at least part of the second electrode extends along the first direction, an orthographic projection of the at least part of the second electrode on the base substrate falls within an orthographic projection of the first body portion of the gate electrode; and
the first direction has an included angle relative to the second direction, and the included angle is greater than 0 degree and less than 90 degrees.

2. The array substrate according to claim 1 , wherein
the first intermediate portion comprises a stripe portion extending along the first direction;
the first electrode comprises:
a plurality of first portions connected with the stripe portion, the plurality of first portions are provided on a first side of the stripe portion near the first body portion, and are spaced apart from each other along the first direction; and
a plurality of second portions connected with the stripe portion, the plurality of second portions are provided on a second side of the stripe portion near the first extension portion, and are spaced apart from each other along the first direction, and

the first overlapping end comprises at least a part of each of the plurality of first portions, and the first compensation end comprises at least a part of each of the plurality of second portions.

3. The array substrate according to claim 2 , wherein each of the plurality of first portions comprises a first region and a second region, an orthographic projection of the first region on the base substrate is within an orthographic projection of the first body portion on the base substrate; an orthographic projection of the second region on the base substrate does not overlap with an orthographic projection of the first body portion on the base substrate, and the orthographic projection of the second region on the base substrate is within an orthographic projection of the first spacing on the base substrate;
each of the plurality of second portions comprises a third region and a fourth region, wherein an orthographic projection of the third region on the base substrate is within an orthographic projection of the first extension portion on the base substrate, and an orthographic projection of the fourth region on the base substrate does not overlap with an orthographic projection of the first extension portion of the first extension on the base substrate, and the orthographic projection of the fourth region on the base substrate is within an orthographic projection of the first spacing on the base substrate.

4. The array substrate according to claim 2 , wherein the plurality of first portions and the plurality of second portions one by one, and the plurality of first portions and the plurality of second portions are axially symmetrical with the stripe portion as an axis of symmetry.

5. The array substrate according to claim 2 , wherein each of the plurality of first portions is perpendicular to the first direction, and each of the plurality of second portions is perpendicular to the first direction.

6. The array substrate according to claim 2 , wherein an orthographic projection of the second electrode on the base substrate at least partially overlaps with the orthographic projection of the first body portion on the base substrate;
the second electrode comprises a plurality of first recessed portions which are arranged in the first direction and recessed in a direction away from the first extension portion, the first electrode further comprises a plurality of first protrusion portions corresponding to the first portions one by one, each of the plurality of first protrusion portions is connected with a corresponding first portion, and the first protrusion portions respectively extend into the first recessed portions one by one; and
the first overlapping end further comprises the plurality of first protrusion portions.

7. The array substrate according to claim 6 , wherein the first body portion has an edge near the first extension portion, and an orthographic projection of the edge on the base substrate at least partially overlaps with orthographic projections of the plurality of first portions on the base substrate, and a width, in the first direction, of each of the first portions is larger than a width, in the first direction, of the first protrusion connected with the respective first portion.

8. The array substrate according to claim 1 , wherein a width of the first extension portion in a direction perpendicular to the first direction is greater than 0 and less than or equal to 3 μm;
a ratio of the width of the first extension portion in the direction perpendicular to the first direction to a width of the first body portion in the direction perpendicular to the first direction is in a range of 0.2-0.3.

9. The array substrate according to claim 1 , and an orthographic projection of the first connection portion on the base substrate does not overlap with both an orthographic projection of the first electrode on the base subs

Assignees

• Hefei Boe Display Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zhang Yuntian
• Rui Zhou
• Jiang Peng
• Yang Haipeng
• Dai Ke
• Zhang Chunxu
• Wu Zhonghou
• Tian Li

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title