Active array matrix substrate of display panel

Patent metadata

Field	Value
Publication number	US-9964822-B2
Application number	US-201514886797-A
Country	US
Kind code	B2
Filing date	Oct 19, 2015
Priority date	Sep 24, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

An active array matrix substrate of a display panel includes a number of scan lines parallel to each other and arranged in a first metal layer of a first substrate, a number of data lines parallel to each other and arranged in a second metal layer of the first substrate, a number of gate electrodes arranged in the first metal layer, a number of source electrodes arranged in the second metal layer, and a number of drain electrodes arranged in the second metal layer. The source electrode includes at least one source extending portion spaced from and configured to overlap with the first metal layer. The drain electrode includes at least one drain extending portion spaced from and configured to overlap with the first metal layer.

First claim

What is claimed is:

1. An active array matrix substrate of a display panel, the active array matrix substrate comprising:
a first substrate;
a plurality of scan lines parallel to each other and arranged in a first metal layer of the first substrate, each pair of scan lines bounding a corresponding row of spaces, each space corresponding in position to a corresponding pixel of the display panel;
a plurality of data lines parallel to each other and arranged in a second metal layer of the first substrate, the plurality of data lines being perpendicular to the plurality of scan lines, and two data lines arranged between every two adjacent columns of spaces;
a plurality of gate electrodes arranged in the first metal layer, each of the plurality of gate electrodes corresponding in position to one corresponding space;
a plurality of source electrodes arranged in the second metal layer, each of the plurality of source electrodes corresponding in position to one corresponding space, and each of the plurality of source electrodes comprising at least one source extending portion spaced apart from and configured to overlap with the first metal layer; and
a plurality of drain electrodes arranged in the second metal layer, each of the plurality of drain electrodes corresponding in position to one corresponding space, and each of the plurality of drain electrodes comprising at least one drain extending portion spaced apart from and configured to overlap with the first metal layer;

wherein the first substrate further comprises:
a gate insulating layer covered over the first metal layer and configured to electrically insulate the plurality of scan lines from the plurality of data lines;
a channel layer arranged on the gate insulating layer and positioned opposite to the plurality of gate electrodes; and
a plurality of pixel electrodes, each of the plurality of pixel electrodes corresponding in position to one corresponding space and configured to receive a corresponding data signal from one corresponding data line;

wherein the source electrode and the drain electrode of each space are arranged on opposite sides of a corresponding portion of the channel layer;
wherein the at least one source extending portion and the first metal layer forms a first capacitor;
wherein the at least one drain extending portion and the first metal layer forms a second capacitor;
wherein each of the plurality of source electrodes is electrically coupled to one corresponding data line;
wherein each of the plurality of gate electrodes is electrically coupled to one corresponding scan line; and
wherein each of the plurality of drain electrodes is electrically coupled to one corresponding pixel electrode;
wherein each of the plurality of source electrodes comprises:
a main body spaced apart from the gate electrode; and
a first connecting portion connected between the main body and the corresponding data line to electrically couple the main body to the corresponding data line;

wherein the source extending portion and the first connecting portion extend from opposite sides of the corresponding data line;
wherein each of the plurality of scan lines comprises a protruding portion arranged between the corresponding two data lines arranged between two adjacent columns of spaces;
wherein the source extending portion overlaps with the protruding portion; and
wherein the source extending portion and the protruding portion cooperatively form the first capacitor.

2. The active array matrix substrate as in claim 1 , wherein:
when an overlapping area between the source electrode and the gate electrode increases, an overlapping area between the source extending portion and the protruding portion decreases; and
when the overlapping area between the source electrode and the gate electrode decreases, the overlapping area between the source extending portion and the protruding portion increases.

3. The active array matrix substrate as in claim 2 , wherein the drain electrode comprises:
an inserting portion spaced from and overlapping with the gate electrode, the inserting portion surrounded by the main body of the source electrode; and
a second connecting portion connected between the inserting portion and the pixel electrode to electrically couple the inserting portion to the pixel electrode.

4. The active array matrix substrate as in claim 3 , wherein:
the drain extending portion is electrically coupled to the inserting portion and the second connecting portion;
the drain extending portion overlaps with the scan line; and
the drain extending portion and the scan line form the second capacitor.

5. The active array matrix substrate as in claim 4 , wherein:
when an overlapping area between the inserting portion and the gate electrode increases, an overlapping area between the drain extending portion and the scan line decreases; and
when the overlapping area between the inserting portion and the gate electrode decreases, the overlapping area between the drain extending portion and the scan line increases.

6. An active array matrix substrate of a display panel, the active array matrix substrate comprising:
a first substrate;
a plurality of scan lines parallel to each other and arranged in a first metal layer of the first substrate, each pair of scan lines bounding a corresponding row of spaces, each space corresponding in position to a corresponding pixel of the display panel;
a plurality of data lines parallel to each other and arranged in a second metal layer of the first substrate, the plurality of data lines being perpendicular to the plurality of scan lines, and two data lines arranged between every two adjacent columns of spaces;
a plurality of gate electrodes arranged in the first metal layer, each of the plurality of gate electrodes corresponding in position to one corresponding space;
a plurality of source electrodes arranged in the second metal layer, each of the plurality of source electrodes corresponding in position to one corresponding space, and each of the plurality of source electrodes comprising at least one source extending portion spaced from and configured to overlap with the first metal layer; and
a plurality of drain electrodes arranged in the second metal layer, each of the plurality of drain electrodes corresponding in position to one corresponding space, and each of the plurality of drain electrodes comprising at least one drain extending portion spaced from and configured to overlap with the first metal layer;

wherein the first substrate comprises:
a gate insulating layer covered over the first metal layer and configured to electrically insulate the plurality of scan lines from the plurality of data lines;
a channel layer arranged on the gate insulating layer and positioned opposite to the plurality of gate electrodes across the gate insulating layer; and
a plurality of pixel electrodes, each of the plurality of pixel electrodes corresponding in position to one corresponding space and configured to receive a corresponding data signal from one corresponding data line;
wherein the source electrode and the data electrode of each space are arranged on opposite sides of a corresponding portion of the channel layer;

wherein the at least one source extending portion and the first metal layer form a first capacitor;
wherein the at least one drain extending portion and the first metal layer forms a second capacitor;
wherein each of the plurality of source electrodes is electrically coupled to one corresponding data line;
wherein each of the plurality of gate electrodes is electrically coupled to one corresponding scan line;
wherein each of the plurality of drain electrodes is electrically coupled to one corresponding pixel electrode;

wherein each of the

Assignees

• Century Tech Shenzhen Corporation Limited

Inventors

• Wang Ming-Tsung
• Liu Chih-Chung
• Cheng Yi-Hsiu
• Chang zhi-hong

Classifications

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/133514

  Colour filters · CPC title

• G02F1/134336

  Matrix · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H01L27/3276

  Electricity · mapped topic