Thin film transistor array panel including angled drain regions

Patent metadata

Field	Value
Publication number	US-9515091-B2
Application number	US-201314099977-A
Country	US
Kind code	B2
Filing date	Dec 8, 2013
Priority date	Jan 4, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.

First claim

What is claimed is:

1. A thin film transistor array panel comprising:
a substrate;
a gate line elongated in a first direction on the substrate, the gate line defining a first gate electrode and a second gate electrode which is spaced apart from the first gate electrode;
a gate insulating layer on the first gate electrode and the second gate electrode;
a semiconductor on the gate insulating layer; and
a source electrode and a unitary drain electrode disposed on the semiconductor,
wherein with reference to a predetermined width in the first direction and a length taken in a second direction perpendicular to the first direction, the unitary drain electrode defines:
a first drain electrode which faces the source electrode with respect to the first gate electrode, the first drain electrode comprising a plurality of first regions thereof sequentially disposed in the first direction and each having a planar area defined by the predetermined width in the first direction and an entirety of the length of the first drain electrode at the predetermined width, and
a second drain electrode which is adjacent to the second gate electrode, the second drain electrode comprising a plurality of second regions thereof sequentially disposed in the first direction and each having a planar area defined by the predetermined width in the first direction and an entirety of the length of the second drain electrode at the predetermined width,
wherein among the plurality of first regions,
a first region among the plurality of first regions comprises an edge which forms an angle from about 0 degrees to about 90 degrees with the first direction, and
the planar area of at least one of the plurality of first regions is different from each planar area of remaining first regions of the plurality of first regions, and

wherein the unitary drain electrode overlapped with the first and second gate electrodes defines,
a first overlapping area by planar areas of the first gate electrode and the first drain electrode overlapping each other and including the first region which comprises the edge which forms the angle from about 0 degrees to about 90 degrees with the first direction, and
a second overlapping area by planar areas of the second gate electrode and the second drain electrode overlapping each other,
wherein the first and second drain electrodes are shaped to maintain a sum of the first and second overlapping areas.

2. The thin film transistor array panel of claim 1 , wherein
a second region among the plurality of second regions of the second drain electrode comprises an edge which forms an angle from about 0 degrees to about 90 degrees with the first direction, and
the planar area of at least one of the plurality of second regions is different from each planar area of remaining second regions of the plurality of second regions.

3. The thin film transistor array panel of claim 2 , wherein
the planar areas of the plurality of first regions and the planar areas of the plurality of second regions one of increase or decrease in the first direction away from the source electrode.

4. The thin film transistor array panel of claim 3 , wherein
the plurality of first regions comprises a first sub-region, a second sub-region and a third sub-region in sequence in the first direction away from the source electrode,
the plurality of second regions comprises a fourth sub-region, a fifth sub-region and a sixth sub-region in sequence in the first direction towards the source electrode,
the planar area of the first sub-region is the same as the planar area of the sixth sub-region,
the planar area of the second sub-region is the same as the planar area of the fifth sub-region, and
the planar area of the third sub-region is the same as the planar area of the fourth sub-region.

5. The thin film transistor array panel of claim 4 , further comprising:
a passivation layer on the source electrode, the first drain electrode and the second drain electrode; and
a pixel electrode on the passivation layer and connected to the first drain electrode through a contact hole defined in the passivation layer.

6. The thin film transistor array panel of claim 5 , further comprising
a common electrode overlapping the pixel electrode; and
an insulating layer between the common electrode and the pixel electrode.

7. The thin film transistor array panel of claim 6 , wherein
one of the pixel electrode and the common electrode comprises a plurality of branch electrodes, and the other of the pixel electrode and the common electrode is plate-shaped.

8. The thin film transistor array panel of claim 1 , wherein
the planar areas of the plurality of first regions and the planar areas of the plurality of second regions one of increase or decrease in the first direction away from the source electrode.

9. The thin film transistor array panel of claim 8 , wherein
the plurality of first regions comprises a first sub-region, a second sub-region and a third sub-region in sequence in the first direction away from the source electrode,
the plurality of second regions comprises a fourth sub-region, a fifth sub-region and a sixth sub-region in sequence in the first direction towards the source electrode,
the planar area of the first sub-region is the same as the planar area of the sixth sub-region,
the planar area of the second sub-region is the same as the planar area of the fifth sub-region, and
the planar area of the third sub-region is the same as the planar area of the fourth sub-region.

10. The thin film transistor array panel of claim 9 , further comprising:
a passivation layer on the source electrode, the first drain electrode and the second drain electrode; and
a pixel electrode on the passivation layer and connected to the first drain electrode through a contact hole defined in the passivation layer.

11. The thin film transistor array panel of claim 10 , further comprising
a common electrode overlapping the pixel electrode; and
an insulating layer between the common electrode and the pixel electrode.

12. The thin film transistor array panel of claim 11 , wherein
one of the pixel electrode and the common electrode comprises a plurality of branch electrodes, and the other the pixel electrode and the common electrode is plate-shaped.

13. The thin film transistor array panel of claim 1 , wherein
the plurality of first regions comprises a first sub-region, a second sub-region and a third sub-region in sequence in the first direction away from the source electrode,
the plurality of second regions comprises a fourth sub-region, a fifth sub-region and a sixth sub-region in sequence in the first direction towards the source electrode,
a planar area of the first sub-region is the same as a planar area of the sixth sub-region,
a planar area of the second sub-region is the same as a planar area of the fifth sub-region, and
a planar area of the third sub-region is the same as a planar area of the fourth sub-region.

14. The thin film transistor array panel of claim 13 , further comprising:
a passivation layer on the source electrode, the first drain electrode and the second drain electrode; and
a pixel electrode on the passivation layer and connected to the first drain electrode through a contact hole defined in the passivation layer.

15. The thin film transistor array panel of claim 14 , further comprising
a common electrode overlapping the pixel electrode; and
an insulating layer between the common electrode and the pixel electrode.

16. The thin film transistor array panel of claim 15 , wherein
one of the pix

Assignees

• Samsung Display Co Ltd

Inventors

• Hwang Jung Hwan
• Koo Bon-Yong
• Park Soo Jin
• Park Jong-Moon
• Lee Yong Hee
• Lee Jong-Hyuk
• Cho Duc-Han

Classifications

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• H10D30/6729 Primary

  characterised by the electrodes · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title