Multi-chain measurement circuit

Patent metadata

Field	Value
Publication number	US-12204287-B2
Application number	US-202217816894-A
Country	US
Kind code	B2
Filing date	Aug 2, 2022
Priority date	Aug 2, 2022
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.

First claim

What is claimed is:

1. An apparatus, comprising:
a measurement circuit, wherein the measurement circuit includes:
a first delay circuit that includes a first set of serially-connected buffer circuits, wherein the first set of serially-connected buffer circuits are configured to propagate an input signal;
a second delay circuit connected in parallel with the first delay circuit, wherein the second delay circuit includes a second set of serially-connected buffer circuits configured to propagate the input signal; and
a set of storage circuits configured to store logic values produced by the first and second sets of buffer circuits in response to a transition of an operating clock signal; and
wherein the measurement circuit is configured to:
use the logic values stored in the set of storage circuits to output a digital value indicative of a total number of serially-connected buffer circuits of the first and second sets of buffer circuits through which the input signal has propagated at a time of the transition of the operating clock signal; and
receive, as the input signal, a supply voltage provided to a functional circuit; and

a power management circuit configured to detect a voltage droop in the supply voltage based on the digital value.

2. The apparatus of claim 1 , wherein a first subset of the set of storage circuits are coupled to selected ones of the first set of serially-connected buffer circuits and wherein a second subset of the set of storage circuits are coupled to selected ones of the second set of serially-connected buffer circuits, and wherein the first set of serially-connected buffer circuits are configured to propagate the input signal at a delay with respect to the second set of serially-connected buffer circuits.

3. The apparatus of claim 2 , wherein ones of the storage circuits are differential flip-flop circuits, wherein ones of the first subset of storage circuits have a first input coupled to an input of a corresponding one of the first set of serially-connected buffer circuits and a second input coupled to an output of the corresponding one of the first set of serially-connected buffer circuits, and wherein ones of the second subset of storage circuit have a first input coupled to an input of a corresponding one of the second set of serially-connected buffer circuits and a second input coupled to an output of the corresponding one of the second set of serially connected buffer circuits.

4. The apparatus of claim 1 , wherein ones of the set of storage circuits are differential storage circuits, and wherein ones of a first subset of the differential storage circuits include a true input coupled to the first delay circuit and a complementary input coupled to the second delay circuit, and wherein ones of a second subset of the differential storage circuits includes a true input coupled to the second delay circuit and a complementary input coupled to the first delay circuit.

5. The apparatus of claim 1 , wherein ones of the set of storage circuits include a first clock input and a second clock input, and wherein:
during operation in a first mode, ones of the set of storage circuits are configured to receive a first clock signal, on their respective first clock input, as the operating clock signal; and
during operation in a second mode, ones of a first subset of the storage circuits are configured to receive, on their respective second clock input, a second clock signal as the operating clock signal and ones of a second subset of the storage circuits are configured to receive, on their second clock input, a third clock signal as the operating clock signal.

6. The apparatus of claim 5 , further comprising a vernier clock circuit having a third delay circuit and a fourth delay circuit, wherein the vernier clock circuit is coupled to receive the second clock signal and is configured to generate the third clock signal that is complementary to and aligned with the second clock signal.

7. The apparatus of claim 6 , wherein the third and fourth delay circuits comprise third and fourth sets of serially-connected buffer circuits, respectively, and wherein ones of the third and fourth sets of serially-connected buffer circuits provide less delay than ones of the first and second sets of serially-connected buffer circuits.

8. The apparatus of claim 5 , further comprising a control circuit configured to cause the measurement circuit to operate in either the first mode or the second mode.

9. The apparatus of claim 1 , further comprising:
a plurality of pairs of cross-coupled inverter circuits coupled between the first set of serially-connected buffer circuits and the second set of serially-connected buffer circuits; and
an edge alignment circuit coupled to the first and second sets of serially-connected buffer circuits, wherein the edge alignment circuit is configured to receive the input signal and further configured to:
generate first and second versions of the input signal based on the input signal, wherein the second version of the input signal is complementary to and aligned with the first version of the input signal.

10. A method comprising:
providing an input signal to a first delay circuit having a first plurality of serially-connected buffer circuits and a second delay circuit having a second plurality of serially-connected buffer circuits;
propagating, in the first plurality of serially-connected buffer circuits, a first signal that is based on the input signal;
propagating, in the second plurality of serially-connected buffer circuits, a second signal that is based on the input signal;
capturing, in ones of a set of storage circuits and in response to a transition of an operating clock signal, logic values produced by the first and second pluralities of serially-connected buffer circuits;
outputting a digital value from the set of storage circuits, wherein the digital value is indicative of a total number of the first and second pluralities of serially-connected buffer circuits through which the input signal had propagated at a time of the transition of the operating clock signal;
receiving, as the input signal, a supply voltage provided to a functional circuit; and
detecting a voltage droop in the supply voltage based on the digital value.

11. The method of claim 10 , further comprising:
providing respective input signals to ones of a first subset of the set of storage circuits from the first plurality of serially-connected buffer circuits; and
providing respective input signals to ones of a second subset of the set of storage circuits from the second plurality of serially-connected buffer circuits; and
wherein the method further includes propagating the input signal in the first plurality of serially-connected buffer circuits at a delay relative to the second plurality of serially-connected buffer circuits.

12. The method of claim 10 , wherein ones of the set of storage circuits are differential storage circuits having respective true and complementary inputs, and wherein the method further comprises:
providing, from ones of the first plurality of serially-connected buffer circuits, respective input signals to the true input of ones of a first subset of the set of storage circuits;
providing, from ones of the second plurality of serially-connected buffer circuits, respective input signals to the complementary input of ones of the first subset of the set of storage circuits;
providing, from ones of the first plurality of serially-connected buffer circuits, respective input signals to the complementary input of ones of a second subset of the set of storage circuits; and
providing, from ones of the second plurality of serially-connected

Assignees

• Apple Inc

Inventors

• Zhao Bo
• Da Silva Cerqueira Joao Pedro
• XU Pangjie
• Lu Steven

Classifications

• H03M1/0836

  of phase error, e.g. jitter · CPC title

• G01R19/255

  using analogue/digital converters of the type with counting of pulses during a period of time proportional to voltage or current, delivered by a pulse generator with fixed frequency · CPC title

• G01R19/16552

  in I.C. power supplies · CPC title

• G01R19/16528

  using digital techniques or performing arithmetic operations (using digital techniques to measure a voltage or a current, see G01R19/25) · CPC title

• G01R19/2513

  Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging · CPC title