Time-to-digital converter using stochastic phase interpolation

Patent metadata

Field	Value
Publication number	US-9490831-B2
Application number	US-201514817727-A
Country	US
Kind code	B2
Filing date	Aug 4, 2015
Priority date	Dec 1, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Provided is a time-to-digital converter. The time-to-digital converter includes several delay circuits, an adder configured to count outputs of the delay circuits, and a least significant bit (LSB) truncation circuit configured to truncate a predetermined number of LSBs from a result output by the adder. The time-to-digital converter is configured to determine a time interval between a start signal and a stop signal within one cycle of a clock having a predetermined period.

First claim

What is claimed is:

1. A time-to-digital converter, comprising:
a plurality of delay circuits;
an adder configured to count outputs of the delay circuits; and
a least significant bit (LSB) truncation circuit configured to truncate a predetermined number of LSBs from a result output by the adder,
wherein the time-to-digital converter is configured to determine a time interval between a start signal and a stop signal within one cycle of a clock signal having a predetermined period.

2. The time-to-digital converter according to claim 1 , wherein the delay circuits are connected in series.

3. The time-to-digital converter according to 2 , wherein each delay circuit comprises:
a delay element having a predetermined time delay;
a logical product operator configured to perform an operation on an output of the delay element, the start signal, and the stop signal, and output a result of the operation; and
a latch configured to latch the output of the logical product operator.

4. The time-to-digital converter according to claim 3 , wherein the clock signal is configured to pass through each delay element.

5. The time-to-digital converter according to claim 2 , wherein the delay circuits generate a number of target bits and the converter further comprises a redundant delay element to output bits more than the number of target bits.

6. A time-to-digital converter, comprising:
a plurality of delay elements configured to transmit a clock signal having a predetermined period;
a plurality of logical product operators connected to outputs of the plurality of delay elements, respectively;
a plurality of latches configured to latch an output of the logical product operators;
an adder configured to count outputs of the plurality of latches; and
a least significant bit (LSB) truncation circuit configured to truncate an output of the adder to generate a target number of bits.

7. The time-to-digital converter according to claim 6 , wherein the delay elements are connected in series.

8. The time-to-digital converter according to claim 7 , wherein the number of the delay elements is larger than the number of target bits.

9. The time-to-digital converter according to claim 7 , wherein the adder counts rising edges of delay signals of the clock signal passing through the delay elements in a predetermined interval between a start signal and a stop signal.

10. The time-to-digital converter according to claim 9 , wherein the start signal and the stop signal are activated and input after passing through all of the delay elements.

11. The time-to-digital converter according to claim 9 , wherein each logical product operator receives and operates on an output of a corresponding one of the delay elements during an interval in which the start signal and the stop signal are activated while overlapping each other.

12. The time-to-digital converter according to claim 9 , wherein the number of the rising edges in the period of the clock signal determines a resolution performance of the time-to-digital converter.

13. The time-to-digital converter according to claim 6 , wherein each logical product operator is an AND gate.

14. A time-to-digital converter configured to generate a digital code indicating a time interval between a start signal and a stop signal, the time-to-digital converter comprising:
a plurality of delay elements connected in series;
a plurality of logic gates, wherein each gate receives the start signal, the stop signal, and an output of a corresponding one of the delay elements;
a plurality of latches, where each latch receives an output of a corresponding one of the logic gates;
an adder configured to add outputs of the latches; and
a circuit configured to truncate an output of the adder to generate the digital code.

15. The time-to-digital converter of claim 14 , wherein the number of delay elements is higher than a total bit count of the digital code.

16. The time-to-digital converter of claim 14 , wherein a first one of the delay elements receives an input of a clock signal, and the adder adds the outputs during a single cycle of the clock signal.

17. The time-to-digital converter of claim 14 , wherein each logic gate is an AND gate.

18. The time-to-digital converter of claim 14 , further comprising:
an even number of delay elements connected in series and configured to output the start signal; and
an odd number of delay elements connected in series and configured to output the stop signal.

19. A digital phase locked loop (PLL) comprising the time-to-digital converter of claim 14 .

20. The digital PLL of claim 19 , further comprising:
a digital loop filter receiving an output of the time-to-digital converter;
a digital controlled oscillator (DCO) receiving an output of the digital loop filter;
a divider circuit performing a division on an output of the DCO to generated a divided signal for output to the time-to-digital converter; and
a crystal oscillator applying a reference signal to the time-to-digital-converter.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sung-Jin
• Kim Jihyun
• Kim Taeik

Classifications

• H03L7/189 Primary

  comprising a D/A converter for generating a coarse tuning voltage · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• Y10S331/02

  Phase locked loop having lock indicating or detecting means · CPC title