Dynamic scaling of system clock signal in response to detection of supply voltage droop

Patent metadata

Field	Value
Publication number	US-11036253-B1
Application number	US-202017039846-A
Country	US
Kind code	B1
Filing date	Sep 30, 2020
Priority date	Sep 30, 2020
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A circuit includes a phase-locked loop configured to receive a reference clock signal and to generate a first clock signal having a first frequency. A secondary clock generation circuit is configured to generate a second clock signal having a second frequency lower than the first frequency. A voltage detection circuit is coupled to receive a supply voltage and configured to detect a droop in the supply voltage and generate a clock control signal in response to detecting a droop in the supply voltage. A selection circuit is coupled to the voltage detection circuit to receive the clock control signal and is configured to select one of the first clock signal and the second clock signal based on the clock control signal.

First claim

What is claimed is:

1. A circuit, comprising:
a phase-locked loop configured to receive a reference clock signal and to generate a first clock signal having a first frequency;
a secondary clock generation circuit configured to generate a second clock signal having a second frequency lower than the first frequency;
a voltage detection circuit coupled to a supply voltage and configured to detect a droop in the supply voltage; and
a selection circuit coupled to the voltage detection circuit,
wherein the selection circuit produces the first clock signal when the voltage detection circuit detects no droop in the supply voltage, and the selection circuit produces the second clock signal when the voltage detection circuit detects a droop in the supply voltage, and
wherein the secondary clock generation circuit is configured to produce a plurality of clock signal frequencies for the second clock signal in response to a clock control signal from the voltage detection circuit.

2. The circuit of claim 1 , further comprising a processor having a power supply input coupled to the supply voltage and a clock input coupled to the selection circuit to receive one of the first clock signal or second clock signal.

3. The circuit of claim 1 , wherein the secondary clock generation circuit comprises a variable oscillator configured to receive an oscillator control input signal to generate the second clock signal.

4. The circuit of claim 1 , wherein the secondary clock generation circuit reduces the clock signal frequency of the second clock signal as the supply voltage decreases.

5. The circuit of claim 1 , wherein the phase-locked loop comprises a proportional path and an integral path, the circuit further comprising:
a first digital-to-analog converter coupled to an output of the voltage detection circuit and configured in the proportional path of the phase-locked loop;
a second digital-to-analog converter coupled to the output of the voltage detection circuit and configured in the integral path of the phase-locked loop;
wherein the first digital-to-analog converter and second digital-to-analog converter generate a first oscillator control input signal to a first variable oscillator to generate the first clock signal;
a third digital-to-analog converter coupled to an output of the voltage detection circuit and configured in the proportional path of the phase-locked loop;
a fourth digital-to-analog converter coupled to the output of the voltage detection circuit and configured in the integral path of the phase-locked loop; and
wherein the third digital-to-analog converter and fourth digital-to-analog converter generate a second oscillator control input signal to a second variable oscillator to generate the second clock signal.

6. The circuit of claim 1 , wherein the voltage detection circuit comprises:
a plurality of resistors coupled in series between a first voltage node configured to receive a first reference voltage and a second reference voltage node, wherein reference nodes are defined at interconnections of the plurality of resistors; and
a plurality of comparators, each of the plurality of comparators having a first input coupled to a corresponding reference node and a second input coupled to receive a sensing voltage indicating a value of the supply voltage.

7. The circuit of claim 1 , wherein the phase-locked loop comprises a first variable oscillator configured to receive a first oscillator control input signal and to generate the first clock signal, and the secondary clock generation circuit comprises a second variable oscillator configured to receive a second oscillator control input signal and to generate the second clock signal.

8. The circuit of claim 7 , wherein the first variable oscillator is configured in the phase locked loop and the first oscillator control input signal is generated in the phase locked loop, and wherein the second variable oscillator is configured in an open loop and the second oscillator control input signal is generated by a digital-to-analog converter.

9. The circuit of claim 7 , wherein the second variable oscillator is a replica oscillator.

10. The circuit of claim 7 , wherein the first and second oscillator control input signals are currents and the first and second variable oscillators are ring oscillators.

11. The circuit of claim 7 , further comprising:
at least one digital-to-analog converter configured to receive at least one signal from the voltage detection circuit and at least one signal from the phase-locked loop, and in accordance therewith, generate the first oscillator control input signal; and
at least one digital-to-analog converter configured to receive at least one signal from the voltage detection circuit and at least one signal from the phase-locked loop, and in accordance therewith, generate the second oscillator control input signal.

12. The circuit of claim 7 , wherein the secondary clock generation circuit selects a first digital signal for configuring a digital-to-analog converter to generate the second oscillator control input signal for the second variable oscillator.

13. A circuit, comprising:
at least one processor;
a phase-locked loop configured to receive a reference clock signal and to generate a first clock signal having a first frequency;
a secondary clock generation circuit configured to generate a second clock signal having a second frequency;
a voltage detection circuit coupled to a supply voltage and configured to detect a droop in the supply voltage; and
a selection circuit coupled to the voltage detection circuit,
wherein at least one of the first frequency and the second frequency are reduced when the voltage detection circuit detects a droop in the supply voltage, and wherein the selection circuit switches between producing the first clock signal and the second clock signal in response to a control signal corresponding to a level of droop in the supply voltage from the voltage detection circuit, and
wherein the first frequency is reduced from an initial frequency and the secondary clock generation circuit is turned on when the supply voltage droops below at least a first threshold voltage, wherein the selection circuit switches from producing the first clock signal to produce the second clock signal having the second frequency equal to the initial frequency when the supply voltage recovers above the first threshold voltage, and wherein the selection circuit switches from producing the second clock signal to produce the first clock signal when the phase-locked loop has stabilized the first clock signal to the initial frequency.

14. The circuit of claim 13 , wherein the first frequency is greater than the second frequency, wherein the second frequency is reduced as the supply voltage decreases.

15. The circuit of claim 13 , wherein the selection circuit switches from producing the first clock signal to produce the second clock signal when the supply voltage droops below a first threshold voltage, and wherein the selection circuit switches from producing the second clock signal to produce the first clock signal when the supply voltage increases above the first threshold voltage.

16. A method of generating a clock for at least one processor, comprising:
generating a first clock signal in a phase-locked loop having a first clock signal frequency;
sensing a supply voltage on the at least one processor;
selecting a second clock signal having a second clock signal frequency, less than the first clock signal frequency, from a secondary clock generation circuit when the supply voltage on the processor is below a first

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Paternoster Paul
• Ippili Sharat

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• G06F1/305 Primary

  in the event of power-supply fluctuations · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title