Driving substrate, method for preparing the same, and display device

Patent metadata

Field	Value
Publication number	US-12199227-B2
Application number	US-202017260778-A
Country	US
Kind code	B2
Filing date	Apr 10, 2020
Priority date	Apr 10, 2020
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

The present disclosure provides a driving substrate, a method for preparing the same, and a display device. The driving substrate includes: a base substrate; a stress buffer layer located on the base substrate; a plurality of first wirings located on a surface of the stress buffer layer away from the base substrate; a first insulating layer located on a surface of the first wiring away from the base substrate; a plurality of second wiring structures located on a surface of the first insulating layer away from the base substrate; a second insulating layer located on a surface of the second wiring structure away from the base substrate; an electronic element located on a surface of the second insulating layer away from the base substrate.

First claim

What is claimed is:

1. A driving substrate, comprising:
a base substrate;
a stress buffer layer located on the base substrate;
a plurality of first wirings located on a surface of the stress buffer layer away from the base substrate, the plurality of first wirings having a first thickness;
a first insulating layer located on a surface of the first wiring away from the base substrate;
a plurality of second wiring structures located on a surface of the first insulating layer away from the base substrate, each of the plurality of first wirings being connected to at least one of the plurality of second wiring structures through a first via hole penetrating through the first insulating layer, the plurality of second wiring structures having a second thickness of more than 6000 angstroms to 9000 angstroms, and the second thickness being less than the first thickness;
a second insulating layer located on a surface of the plurality of second wiring structures away from the base substrate, wherein the second insulating layer comprises an inorganic insulating layer and an organic insulating layer located on a surface of the inorganic insulating layer away from the base substrate; and
an electronic element located on a surface of the second insulating layer away from the base substrate, the electronic element being directly connected to the plurality of second wiring structures through at least two second via holes penetrating through the second insulating layer, and an orthographic projection of the electronic element on the base substrate partially overlaps with orthographic projections of the plurality of second wiring structures on the base substrate,
wherein an aperture of an orthogonal projection of the first via hole on the base substrate is not greater than a line width of an orthogonal projection of the first wiring on the base substrate; an aperture of an orthogonal projection of the second via hole on the base substrate is not greater than a line width of an orthogonal projection of the second wiring on the base substrate.

2. The driving substrate of claim 1 , wherein the first wiring comprises a copper layer and a first metal layer that are stacked, the first metal layer is located on a surface of the copper layer proximate to the base substrate, and an adhesion force between the first metal layer and the stress buffer layer is greater than an adhesion force between the copper layer and the stress buffer layer.

3. The driving substrate of claim 2 , wherein the copper layer has a thickness in a range from 1 to 30 μm.

4. The driving substrate of claim 2 , wherein the first wiring further comprises a first conductive protection layer located on a surface of the copper layer proximate to the base substrate.

5. The driving substrate of claim 1 , wherein the second wiring structure comprises at least one second wiring layer, and each of the at least one second wiring layer comprises a plurality of second wirings, in a situation that the at least one second wiring layer comprises several second wiring layers, an insulating layer is arranged between two adjacent second wiring layers, and in a direction away from the base substrate, each of the second wirings in a previous second wiring layer is connected to at least one of the second wirings in a next second wiring layer, and each of the second wirings in the last second wiring layer is connected to at least one of the electronic elements.

6. The driving substrate of claim 5 , wherein the second wiring comprises a copper layer and a second metal layer that are stacked, the second metal layer is located on a surface of the copper layer proximate to the base substrate, and an adhesion force between the second metal layer and the first insulating layer is greater than an adhesion force between the copper layer and the first insulating layer.

7. The driving substrate of claim 5 , wherein the driving substrate comprises a display area and a fan-out area located at a periphery of the display area, and the driving substrate further comprises:
a second conductive protection layer covering the second wiring of the fan-out area.

8. The driving substrate of claim 1 , wherein the first insulating layer comprises:
a first inorganic insulating layer and a first organic insulating layer that are stacked, the first organic insulating layer being located on a surface of the first inorganic insulating layer away from the base substrate.

9. The driving substrate of claim 8 , wherein the driving substrate further comprises:
a fourth inorganic insulating layer located on the surface of the first organic insulating layer away from the base substrate, the second wiring structure being located on a surface of the fourth inorganic insulating layer away from the base substrate.

10. A display device, comprising the driving substrate of claim 1 .

11. The display device of claim 10 , wherein the first wiring comprises a copper layer and a first metal layer that are stacked, the first metal layer is located on a surface of the copper layer proximate to the base substrate, and an adhesion force between the first metal layer and the stress buffer layer is greater than an adhesion force between the copper layer and the stress buffer layer.

12. The display device of claim 11 , wherein the copper layer has a thickness in a range from 1 to 30 μm.

13. The display device of claim 11 , wherein the first wiring further comprises a first conductive protection layer located on a surface of the copper layer proximate to the base substrate.

14. A method for preparing a driving substrate, comprising:
providing a base substrate;
forming a stress buffer layer on the base substrate;
forming a plurality of first wirings on the stress buffer layer through a single patterning process, the plurality of first wirings having a first thickness;
forming a first insulating layer covering the first wiring, the first insulating layer comprising a first via hole exposing a part of a surface of the first wiring;
forming a plurality of second wiring structures on the first insulating layer, each of the plurality of first wirings being connected to at least one of the plurality of second wiring structures through the first via hole penetrating through the first insulating layer, the plurality of second wiring structures having a second thickness of more than 6000 angstroms to 9000 angstroms, and the second thickness being less than the first thickness;
forming a second insulating layer covering the plurality of second wiring structures, the second insulating layer comprising at least two second via holes exposing a part of a surface of the second wiring structure, wherein the second insulating layer comprises an inorganic insulating layer and an organic insulating layer located on a surface of the inorganic insulating layer away from the base substrate; and
forming an electronic element on the second insulating layer, the electronic element being directly connected to the plurality of second wiring structures through the at least two second via holes penetrating through the second insulating layer, and an orthographic projection of the electronic element on the base substrate partially overlaps with orthographic projections of the plurality of second wiring structures on the base substrate,
wherein an aperture of an orthogonal projection of the first via hole on the base substrate is not greater than a line width of an orthogonal projection of the first wiring on the base substrate; an aperture of an orthogonal projection of the second via hole on the base substrate is not greater than a line width of an orthogonal projection of the second wiring

Assignees

• Boe Technology Group Co Ltd

Inventors

• Cao Zhanfeng
• Wang Ke
• Wang Jianguo
• Zhang Guocai
• Yuan Guangcai
• Dong Xue

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10H20/0364

  of interconnections · CPC title

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title