Plugs for interconnect lines for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-12199168-B2
Application number	US-202217849198-A
Country	US
Kind code	B2
Filing date	Jun 24, 2022
Priority date	Nov 30, 2017
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
an inter-layer dielectric (ILD) layer above a substrate;
a conductive interconnect structure in a trench in the ILD layer, the conductive interconnect structure having a first conductive line and a second conductive line, an end of the first conductive line laterally spaced apart and electrically isolated from an end of the second conductive line, wherein the first and second conductive lines of the conductive interconnect structure have a bottom on the ILD layer, and wherein the first and second conductive lines of the conductive interconnect structure have a top surface; and
a dielectric plug between and in lateral contact with the ends of the first and second conductive lines of the conductive interconnect structure, the dielectric plug comprising a metal oxide material, wherein the dielectric plug has a bottom on the ILD layer and has a top surface, the top surface of the dielectric plug substantially co-planar with the top surface of the first and second conductive lines of the conductive interconnect structure.

2. The integrated circuit structure of claim 1 , wherein the metal oxide material is aluminum oxide.

3. The integrated circuit structure of claim 1 , wherein the dielectric plug has an approximately vertical seam spaced approximately equally from the first conductive line of the conductive interconnect structure and from the second conductive line of the conductive interconnect structure.

4. The integrated circuit structure of claim 1 , further comprising:
a first conductive via in a second trench in the ILD layer, the first conductive via below the bottom of the first conductive line, and the first conductive via electrically coupled to the first conductive line; and
a second conductive via in a third trench in the ILD layer, the second conductive via below the bottom of the second conductive line, and the second conductive via electrically coupled to the second conductive line.

5. The integrated circuit structure of claim 1 , wherein the first and second conductive lines of the conductive interconnect structure comprise a conductive barrier liner and a conductive fill material, the conductive fill material comprising cobalt.

6. An integrated circuit structure, comprising:
a first plurality of conductive interconnect structures in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect structures have a dielectric plug in lateral contact with and electrically isolating corresponding ends of conductive lines, wherein the conductive lines have a bottom on the first ILD layer and have a top surface, the dielectric plug having a bottom on the first ILD layer and having a top surface, the top surface of the dielectric plug substantially co-planar with the top surface of of the conductive lines, and the dielectric plug comprising a material different than the ILD layer; and
a second plurality of conductive interconnect structures in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect structures have conductive lines having ends separated by the second ILD layer.

7. The integrated circuit structure of claim 6 , wherein the dielectric plug comprise a metal oxide material.

8. The integrated circuit structure of claim 7 , wherein the metal oxide material is aluminum oxide.

9. The integrated circuit structure of claim 8 , wherein the first ILD layer and the second ILD layer comprise a carbon-doped silicon oxide material.

10. The integrated circuit structure of claim 6 , wherein the conductive lines of the the first plurality of conductive interconnect structures comprise a first conductive barrier liner and a first conductive fill material, the second plurality of conductive interconnect structures comprise a second conductive barrier liner and a second conductive fill material, and wherein the first conductive fill material is different in composition from the second conductive fill material.

11. The integrated circuit structure of claim 10 , wherein the first conductive fill material comprises cobalt, and the second conductive fill material comprises copper.

12. The integrated circuit structure of claim 6 , wherein the conductive lines of the first plurality of conductive interconnect structures have a first pitch, the conductive lines of the second plurality of conductive interconnect structures have a second pitch, and wherein the second pitch is greater than the first pitch.

13. The integrated circuit structure of claim 6 , wherein the conductive lines of the first plurality of conductive interconnect structures have a first width, the conductive lines of the second plurality of conductive interconnect structures have a second width, and wherein the second width is greater than the first width.

14. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
an inter-layer dielectric (ILD) layer above a substrate;
a conductive interconnect structure in a trench in the ILD layer, the conductive interconnect structure having a first conductive line and a second conductive line, an end of the first conductive line laterally spaced apart and electrically isolated from an end of the second conductive line, wherein the first and second conductive lines of the conductive interconnect structure have a bottom on the ILD layer, and wherein the first and second conductive lines of the conductive interconnect structure have a top surface; and
a dielectric plug between and in lateral contact with the ends of the first and second conductive lines of the conductive interconnect structure, the dielectric plug comprising a metal oxide material, wherein the dielectric plug has a bottom on the ILD layer and has a top surface, the top surface of the dielectric plug substantially co-planar with the top surface of the first and second conductive lines of the conductive interconnect structure.

15. The computing device of claim 14 , further comprising:
a memory coupled to the board.

16. The computing device of claim 14 , further comprising:
a communication chip coupled to the board.

17. The computing device of claim 14 , wherein the component is a packaged integrated circuit die.

18. The computing device of claim 14 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Yeoh Andrew W
• Jin Ilsup
• Kandas Angelo
• Hattendorf Michael L
• Auth Christopher P

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title