Covers for semiconductor package components

Patent metadata

Field	Value
Publication number	US-12198995-B2
Application number	US-202318484321-A
Country	US
Kind code	B2
Filing date	Oct 10, 2023
Priority date	Dec 9, 2020
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.

First claim

What is claimed is:

1. A method of making a semiconductor package, comprising:
positioning a cover on a semiconductor die to cover an operational component of the semiconductor die, such that a hollow area is in between the cover and the operational component, wherein a perimeter of the cover is proximate to the operational component than a perimeter of the semiconductor die;
positioning the semiconductor die and the cover in a mold chase;
positioning a member of the mold chase so that the member does not contact the cover; and
introducing a mold compound into the mold chase to cover the semiconductor die and the cover, the cover precluding the mold compound from contacting the operational component.

2. The method of claim 1 further comprising, prior to positioning the cover, providing an inert atmosphere at an operational component of a semiconductor die.

3. The method of claim 1 , wherein the cover forms a hermetic seal around at least part of the operational component.

4. The method of claim 1 , wherein the cover forms a hermetic seal around the operational component between a surface of the cover and the semiconductor die.

5. The method of claim 1 , wherein the cover comprises metal and is coupled to the semiconductor die with solder.

6. The method of claim 1 , wherein the operational component is positioned closer to a center of the semiconductor die than to an edge of the semiconductor die.

7. The method of claim 1 , wherein the operational component is located at a center of the semiconductor die.

8. The method of claim 1 , wherein the cover comprises one of a rectangular horizontal cross-sectional shape, a circular horizontal cross-sectional shape, a rectangular horizontal cross-sectional shape with rounded corners; and a cross-shaped horizontal cross-sectional shape.

9. The method of claim 1 , wherein a vertical dimension of the cover does not exceed 1 millimeter.

10. The method of claim 1 , wherein the cover includes a monolithic structure including a vertical portion and a horizontal portion.

11. A method of making a semiconductor package, comprising:
positioning a cover on a semiconductor die to cover an operational component of the semiconductor die, such that a hollow area is formed between the cover and the operational component, wherein the cover includes a monolithic structure including a vertical portion and a horizontal portion, a perimeter of the cover along the vertical portion being closer to the operational component than an edge of the semiconductor die;
positioning the semiconductor die and the cover in a mold chase; and
introducing a mold compound into the mold chase to cover the semiconductor die and the cover, the cover precluding the mold compound from contacting the operational component.

12. The method of claim 11 , wherein positioning the cover on the semiconductor die to cover the operational component includes attaching the cover to a top surface of the semiconductor die using a metal or a metal alloy.

13. The method of claim 11 , wherein the operational component is a precision circuit of the semiconductor die.

14. A method of making a semiconductor package, comprising:
attaching a semiconductor die to a lead frame and electrically connecting the semiconductor die to leads of the lead frame;
attaching a cover on the semiconductor die over an operational component of the semiconductor die, such that a hollow area is between the cover and the operational component, wherein the cover includes a monolithic structure including a vertical portion and a horizontal portion, a perimeter of the cover along the vertical portion being closer to the operational component than an edge of the semiconductor die;
positioning the semiconductor die and the cover in a mold chase; and
introducing a mold compound into the mold chase to cover the semiconductor die and the cover, the cover precluding the mold compound from contacting the operational component.

15. The method of claim 14 , wherein the cover comprises one of a rectangular horizontal cross-sectional shape, a circular horizontal cross-sectional shape, a rectangular horizontal cross-sectional shape with rounded corners; and a cross-shaped horizontal cross-sectional shape.

16. The method of claim 14 , wherein a vertical dimension of the cover does not exceed 1 millimeter.

17. The semiconductor package of claim 14 , wherein the hollow area is inert.

18. The semiconductor package of claim 14 , wherein the cover is attached to an active surface of the semiconductor die.

19. The semiconductor package of claim 14 , wherein the cover is attached to the semiconductor die with a metal or metal alloy.

20. The semiconductor package of claim 14 , wherein the cover is attached to the semiconductor die with an adhesive.

Assignees

• Texas Instruments Inc

Inventors

• Koduri Sreenivasan Kalyani
• Stark Leslie Edward

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W70/40

  Leadframes · CPC title

• H10W74/124 Primary

  the encapsulations having cavities other than that occupied by chips · CPC title

• H10W74/01

  Manufacture or treatment · CPC title