Contact over active gate structure

Patent metadata

Field	Value
Publication number	US-12198985-B2
Application number	US-202217875527-A
Country	US
Kind code	B2
Filing date	Jul 28, 2022
Priority date	Aug 31, 2018
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.

First claim

What is claimed is:

1. An electronic device comprising:
a substrate having an active region with at least one gate stack formed thereon, the at least one gate stack having a first side and a second side and comprising a gate and a gate cap on the gate, the gate cap comprising a first material;
a spacer material on the substrate adjacent the first side and the second side of the at least one gate stack;
a source material with a source cap on the source material, the source cap comprising a second material, the source material and the source cap adjacent one of a first side or a second side of the spacer material;
a drain material with a drain cap on the drain material, the drain cap comprising the second material, the drain material and the drain cap adjacent the other of the first side or the second side of the spacer material;
a fill material directly on a portion of the drain material in contact with the drain cap or directly on a portion of the source material in contact with the source cap, the fill material having a top surface substantially coplanar with a top surface of the spacer material, and substantially coplanar with one or more of a top surface of the drain cap or a top surface of the source cap; and
an interlayer dielectric (ILD) on the top surface of one or more of the spacer material, the gate cap, the drain cap, or the source cap.

2. The electronic device of claim 1 , wherein the fill material is selected from one or more of hafnium oxide, zirconium oxide, aluminum oxide, silicon oxide, silicon nitride, or the like.

3. The electronic device of claim 1 , wherein the gate comprises a metal selected from one or more of cobalt, tungsten, titanium, molybdenum, nickel, ruthenium, silver, iridium, or platinum.

4. The electronic device of claim 1 , wherein the first material comprises one or more of silicon carbide, tungsten oxide, tungsten carbide, silicon nitride, aluminum oxide, or zirconium oxide.

5. The electronic device of claim 1 , wherein the spacer material comprises a low-K dielectric.

6. The electronic device of claim 5 , wherein the low-K dielectric comprises one or more of silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride.

7. The electronic device of claim 1 , wherein the second material comprises one or more of silicon nitride, silicon oxynitride, or silicon oxide.

8. The electronic device of claim 1 , further comprising a first mask layer on the interlayer dielectric (ILD).

9. The electronic device of claim 8 , wherein the first mask layer comprises a third material selected from one or more of a spin-on carbon, hardmask, or a photoresist.

10. The electronic device of claim 1 , further comprising one or more of a gate contact and a source/drain contact, the gate contact on a top surface of one or more of the gate, the source material, or the drain material, and the source/drain contact on one or more of the gate cap, the source material, or the drain material.

11. The electronic device of claim 10 , wherein the gate contact and the source/drain contact independently comprises one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), or platinum (Pt).

Assignees

• Applied Materials Inc

Inventors

• Wang Wenhui
• Dai Huixiong
• Ngai Christopher S

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10D64/01

  Manufacture or treatment · CPC title