Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2017194211-A1
Application number	US-201615157200-A
Country	US
Kind code	A1
Filing date	May 17, 2016
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
forming gate structures extending in a first direction and arranged in a second direction crossing the first direction, each of the gate structures including a gate electrode, a gate cap insulating layer disposed over the gate electrode, sidewall spacers disposed on opposing side faces of the gate electrode and the gate cap insulating layer; forming source/drain structures between adjacent two gate structures, each of the source/drain structures including a source/drain conductive layer and a source/drain cap insulating layer disposed on the source/drain conductive layer; selectively removing the gate cap insulating layer from at least one of the gate structures, while protecting at least one of remaining gate structures, thereby exposing the gate electrode of the at least one of the gate structures; selectively removing the source/drain cap insulating layer from at least one of the source/drain structures, while protecting at least one of remaining source/drain structures, thereby exposing the source/drain conductive layer of the at least one of the source/drain structures; and forming conductive contact layers on the exposed gate electrode and the exposed source/drain conductive layer.

2 . The method of claim 1 , wherein in the selectively removing the gate cap insulating layer, at least one source/drain cap insulating layer is not protected.

3 . The method of claim 1 , wherein in the selectively removing the source/drain cap insulating layer, at least one gate insulating layer is not protected.

4 . The method of claim 1 , wherein:
in the selectively removing the gate cap insulating layer, the at least one of remaining gate structures is protected by a protective pattern, and an edge of the protective pattern is located on at least one source/drain cap insulating layer.

5 . The method of claim 1 , wherein:
in the selectively removing the source/drain cap insulating layer, the at least one of remaining source/drain structures is protected by a protective pattern, and an edge of the protective pattern is located on at least one gate cap insulating layer.

6 . The method of claim 1 , wherein an upper surface of the gate electrode is located at a different level from an upper surface of the source/drain conductive layer.

7 . The method of claim 6 , wherein the upper surface of the gate electrode is located at a lower level than the upper surface of the source/drain conductive layer.

8 . The method of claim 1 , wherein the gate cap insulating layer is made of different material than the source/drain cap insulating layer.

9 . The method of claim 8 , wherein the gate cap insulating layer and the source/drain cap insulating layer are made of at least one of SiC, SiOCN, SiON, SiCN and SiN.

10 . The method of claim 1 , wherein the sidewall spacers are made of different material than the gate cap insulating layer and the source/drain cap insulating layer.

11 . The method of claim 10 , wherein the sidewall spacers are made of at least one of SiC, SiON, Al 2 O 3 , SiOCN, SiCN and SiN.

12 . A method of manufacturing a semiconductor device, the method comprising:
forming a first gate structure, a second gate structure, a third gate structure and a fourth gate structure, which extend in a first direction, over a substrate, the first gate structure including a first gate electrode, a first gate dielectric layer, first sidewall spacers disposed on opposing side faces of the first gate electrode, the second gate structure including a second gate electrode, a second gate dielectric layer, second sidewall spacers disposed on opposing side faces of the second gate electrode, the third gate structure including a third gate electrode, a third gate dielectric layer, third sidewall spacers disposed on opposing side faces of the third gate electrode, the fourth gate structure including a fourth gate electrode, a fourth gate dielectric layer, fourth sidewall spacers disposed on opposing side faces of the fourth gate electrode, the first to the fourth gate structures being arranged in a second direction crossing the first direction; forming a first source/drain region between the first and second gate structures, a second source/drain region between the second and third gate structures, and a third source/drain region between the third and fourth gate structures; forming a first insulating layer over the first to third source/drain regions; recessing the first to fourth gate electrodes below upper surfaces of the first to fourth sidewall spacers, thereby forming a first to a fourth gate opening, respectively; forming a first to a fourth gate cap insulating layer in the first to the fourth gate openings, respectively; removing the first insulating layer so as to expose the first and third source/drain regions; forming a first and a third source/drain conductive layers over the first and third source/drain regions, respectively; recessing the first and the third source/drain conductive layers below upper surfaces of the first to fourth sidewall spacers, thereby forming a first and a third source/drain opening, respectively; forming a first and a third source/drain cap insulating layer in the first and the third source/drain openings, respectively; removing the first and second gate cap insulating layers, while protecting the third and fourth gate cap insulating layers and the third source/drain cap insulating layer, thereby exposing the first and second gate electrodes; removing the third source/drain cap insulating layer, while protecting the first source/drain cap insulating layer, thereby exposing the third source/drain region; and forming conductive contact layers on the exposed first and second gate electrodes and the exposed third source/drain region.

13 . The method of claim 12 , wherein in the removing the first insulating layer so as to expose the first and third source/drain regions, the second source/drain region is protected and the first insulating layer formed over the second source/drain region is not removed.

14 . The method of claim 12 , wherein:
the first to fourth gate cap insulating layers are made of different material than the first and third source/drain cap insulating layers, the first to fourth gate cap insulating layers and the first and third source/drain cap insulating layers are made of at least one of SiC, SiON, SiOCN, SiCN and SiN, the first to fourth sidewall spacers are made of different material than the first to the fourth gate cap insulating layers and the first and third source/drain cap insulating layer, and the first to fourth sidewall spacers are made of at least one of SiC, SiON, Al 2 O 3 , SiOCN, SiCN and SiN.

15 . A semiconductor device comprising:
a first gate structure including a first gate electrode and a first cap insulating layer disposed on the first gate electrode; a second gate structure including a second gate electrode and a first conductive contact layer disposed on the first gate electrode; a first source/drain structure including a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer; and a second source/drain structure including a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.

16 . The semiconductor device of claim 15 , wherein an upper surface of the first gate electrode is located at a different level from an upper surface of the first source/drain conducti

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Jui-Yao
• Liu Ru-Gun
• Yeong Sai-Hooi
• Chen Yen-Ming
• Yen Yung-Sung
• Chen Ying-Yan

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title