Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12198767-B2
Application number	US-202318243258-A
Country	US
Kind code	B2
Filing date	Sep 7, 2023
Priority date	Nov 6, 2018
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

A semiconductor memory device according to an embodiment includes a plurality of planes each including a plurality of blocks each including a memory cell, an input/output circuit configured to receive a command set from an external controller, and a sequencer configured to execute an operation in response to the command set. Upon receiving a first command set that instructs execution of a first operation, the sequencer executes the first operation. Upon receiving a second command set that instructs execution of a second operation during execution of the first operation, the sequencer executes the second operation in parallel with the first operation. Upon receiving a third command set that instructs execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.

First claim

The invention claimed is:

1. A semiconductor memory device comprising:
a first plane including a plurality of first blocks, each of the first blocks including a first memory cell:
a second plane including a plurality of second blocks, each of the second blocks including a second memory cell;
a voltage generator which includes a first driver configured to supply power to the first plane and a second driver configured to supply power to the second plane;
an input/output circuit configured to receive a command set from an external memory controller; and
a sequencer configured to execute an operation in response to the command set,
wherein:
upon receiving a first command set that instructs execution of a first operation to the first memory cell of one of the first blocks, the sequencer executes the first operation, the first operation causing a change of a threshold voltage of the first memory cell of the one of the first blocks,
upon receiving a second command set that instructs execution of a second operation to the second memory cell of one of the second blocks during execution of the first operation, the sequencer executes the second operation in parallel with the first operation, and
upon receiving a third command set that instructs execution of a third operation to the first memory cell of another one of the first blocks during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.

2. The semiconductor memory device of claim 1 , wherein:
the second operation does not cause a change of a threshold voltage of the second memory cell of the one of the second blocks, and
the third operation does not cause a change of a threshold voltage of the first memory cell of the another one of the first blocks.

3. The semiconductor memory device of claim 1 , wherein:
in each of the first blocks, a plurality of the first memory cells are connected in series to form a first NAND string,
in each of the second blocks, a plurality of the second memory cells are connected in series to form a second NAND string,
the first operation causes a change of the threshold voltages of the first memory cells belonging to the first NAND string of the one of the first blocks,
the second operation accesses one of the second memory cells belonging to the second NAND string of the one of the second blocks, and
the third operation accesses one of the first memory cells belonging to the first NAND string of the another one of the first blocks.

4. The semiconductor memory device of claim 3 , wherein:
the first operation is an erase operation, and
each of the second operation and the third operation is a read operation.

5. The semiconductor memory device of claim 4 , wherein a timing at which the sequencer executes the second operation upon receiving the second command set during the execution of the first operation changes based on a timing at which the second command set is received.

6. The semiconductor memory device of claim 4 , wherein the first operation is resumed regardless of an instruction from the external memory controller after data read by the second operation has been output.

7. The semiconductor memory device of claim 4 , wherein the first operation is resumed based on an external command that has been received after data read by the second operation has been output.

8. The semiconductor memory device of claim 3 , further comprising:
a first bit line connected to first ends of the first NAND strings of the first blocks; and
a second bit line connected to first ends of the second NAND strings of the second blocks.

9. The semiconductor memory device of claim 8 , further comprising:
a first source line connected to second ends of the first NAND strings of the first blocks; and
a second source line connected to second ends of the second NAND strings of the second blocks.

10. The semiconductor memory device of claim 1 , further comprising:
a third plane including a plurality of third blocks, each of the third blocks including a third memory cell; and
a fourth plane including a plurality of fourth blocks, each of the fourth blocks including a fourth memory cell,
wherein:
the first driver is configured to supply power to the first plane and the third plane, and
the second driver is configured to supply power to the second plane and the fourth plane.

11. The semiconductor memory device of claim 10 , wherein:
in each of the first blocks, a plurality of the first memory cells are connected in series to form a first NAND string,
in each of the second blocks, a plurality of the second memory cells are connected in series to form a second NAND string,
in each of the third blocks, a plurality of the third memory cells are connected in series to form a third NAND string, and
in each of the fourth blocks, a plurality of the fourth memory cells are connected in series to form a fourth NAND string.

12. The semiconductor memory device of claim 11 , further comprising:
a first bit line connected to first ends of the first NAND strings of the first blocks;
a second bit line connected to first ends of the second NAND strings of the second blocks;
a third bit line connected to first ends of the third NAND strings of the third blocks;
a fourth bit line connected to first ends of the fourth NAND strings of the fourth blocks;
a first source line connected to second ends of the first NAND strings of the first blocks;
a second source line connected to second ends of the second NAND strings of the second blocks;
a third source line connected to second ends of the third NAND strings of the third blocks; and
a fourth source line connected to the second ends of the fourth NAND strings of the fourth blocks.

13. The semiconductor memory device of claim 12 , wherein:
during the first operation, the first driver applies an erase voltage to the first source line, and
upon receiving the second command set during the execution of the first operation, the sequencer executes the second operation in parallel with the first operation without discharging the first source line.

14. The semiconductor memory device of claim 13 , wherein upon receiving the third command set during the execution of the first operation, the sequencer suspends the first operation while discharging the first source line, executes the third operation, and resumes the first operation upon completion of the third operation.

15. The semiconductor memory device of claim 14 , wherein:
during the first operation, the first driver applies an erase voltage to the first source line, and
upon receiving a fourth command set that instructs execution of a fourth operation to one of the third memory cells of the third NAND string of one of the third blocks during execution of the first operation, the sequencer suspends the first operation without discharging the first source line, executes the fourth operation, and resumes the first operation upon completion of the third operation.

Assignees

• Kioxia Corp

Inventors

• Sugahara Akio
• Imamoto Akihiro
• Watanabe Toshifumi
• Kakoi Mami
• Masuda Kohei
• Yoshihara Masahiro
• Abiko Naofumi

Classifications

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C2216/20

  Suspension of programming or erasing cells in an array in order to read other cells in it · CPC title