Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10249377-B2
Application number	US-201715700864-A
Country	US
Kind code	B2
Filing date	Sep 11, 2017
Priority date	Feb 27, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a word line, and a row decoder. A write operation repeats a program loop including a program operation, first and second verify operations. The row decoder applies a first read voltage to the word line in the first and second verify operations. When the write operation is not suspended, the sense amplifier senses a voltage of the bit line for a first sense period in the first verify operation. When the write operation is suspended, the sense amplifier senses the voltage of the bit line for a second sense period shorter than the first sense period in the initial first verify operation after a resumption of the write operation.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell;
a bit line coupled to the memory cell;
a sense amplifier coupled to the bit line;
a word line coupled to a gate of the memory cell; and
a row decoder coupled to the word line,
wherein a write operation repeats a program loop including a program operation, a first verify operation performed after the program operation, and a second verify operation performed after the first verify operation,
the row decoder applies a first read voltage to the word line in the first and second verify operations,
when the write operation is not suspended, the sense amplifier senses a voltage of the bit line for a first sense period in the first verify operation,
when the write operation is suspended, the sense amplifier senses the voltage of the bit line for a second sense period shorter than the first sense period in the initial first verify operation after a resumption of the write operation, and
the sense amplifier senses the voltage of the bit line for a third sense period longer than the first sense period in the second verify operation.

2. The device according to claim 1 , wherein the write operation is suspended before the first verify operation is performed after the program operation, and is resumed from the first verify operation.

3. The device according to claim 1 , wherein the write operation is suspended before the program operation in the next program loop is executed after the second verify operation, and is resumed from the first verify operation.

4. The device according to claim 1 , wherein the write operation is suspended before the end of the second verify operation after at least a part of the first verify operation or the second verify operation is performed, and is resumed from the first verify operation.

5. The device according to claim 1 , wherein in the write operation, the write operation is suspended when a suspend command to suspend the write operation is received, and the write operation is resumed when a resume command to resume the write operation is received.

6. The device according to claim 1 , wherein the program operation includes a first program condition to apply a first voltage to the bit line when the first verify operation is failed, and a second program condition to apply a second voltage higher than the first voltage to the bit line when the first verify operation is passed and the second verify operation is failed.

7. The device according to claim 1 , wherein the row decoder applies a program voltage to the word line in the program operation, and
the program voltage is stepped up every time the program loop is repeated.

8. The device according to claim 1 , wherein the row decoder applies a program voltage to the word line in the program operation,
when the write operation is not suspended, the program voltage is stepped up every time the program loop is repeated, and
when the write operation is suspended, the first program voltage after the resumption of the write operation is the same as the last program voltage before the write operation is suspended.

9. The device according to claim 6 , wherein in the write operation, the second program condition is applied only once for the memory cell.

10. The device according to claim 6 , wherein the program loop further includes a third verify operation performed after the second verify operation, and a fourth verify operation performed after the third verify operation,
the row decoder applies a second read voltage higher than the first read voltage to the word line when the third and fourth verify operations are performed,
the first program condition is applied when the first verify operation or the third verify operation is failed,
the second program condition is applied when the first verify operation is passed and the second verify operation is failed or when the third verify operation is passed and the fourth verify operation is failed,
when the write operation is not suspended, the sense amplifier senses the voltage of the bit line for a fourth sense period in the third verify operation,
when the write operation is suspended, the sense amplifier senses the voltage of the bit line for a fifth sense period shorter than the fourth sense period in the initial third verify operation after the resumption of the write operation, and
the sense amplifier senses the voltage of the bit line for a sixth sense period longer than the fourth sense period in the fourth verify operation.

Assignees

• Toshiba Memory Corp

Inventors

• Kasai Hayao
• Nagao Osamu
• Honma Mitsuaki
• Harada Yoshikazu
• Sugahara Akio

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title