Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Patent metadata

Field	Value
Publication number	US-10379738-B2
Application number	US-201715854622-A
Country	US
Kind code	B2
Filing date	Dec 26, 2017
Priority date	Nov 5, 2015
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory array comprising a plurality of memory planes, wherein each of the plurality of memory planes comprises a plurality of memory cells;
a plurality of read level voltage regulator circuits, wherein each read level voltage regulator circuit of the plurality of read level voltage regulator circuits is configured to provide a respective read level voltage signal for a corresponding memory plane of the plurality of memory planes;
a controller configured to perform concurrent memory access operations on two or more of the plurality of memory planes, wherein, during the concurrent memory access operations, the controller is configured to control two or more of the plurality of read level voltage regulator circuits to provide the respective read level voltage signal; and
a plurality of global access line decoder circuits, wherein a global access line decoder circuit of the plurality of global access line decoder circuits is coupled to a respective memory plane of the plurality of memory planes via a respective global access line bus, wherein, during a memory access operation, the global access line decoder circuit of the plurality of global access line decoder circuits is configured to provide the respective read level voltage signal to one of a plurality of global access lines of the respective global access line bus, wherein the global access line decoder circuit of the plurality of global access line decoder circuits is further configured to provide a respective pass voltage signal on each remaining global access line of the plurality of global access lines of the respective global access line bus.

2. The apparatus of claim 1 , wherein the controller is further configured to control the two or more of the plurality of read level voltage regulator circuits to provide a read level voltage signal having a common prologue voltage profile and a common epilogue voltage profile that bookend an independent read level voltage profile selected.

3. The apparatus of claim 2 , wherein the independent read level voltage profile selected is based on a targeted page type during a read operation.

4. The apparatus of claim 1 , wherein each read level voltage has a voltage profile associated with a respective page type.

5. The apparatus of claim 1 , wherein each read level voltage regulator circuit of the plurality of read level voltage regulator circuits is configured to provide the respective read level voltage signal for the corresponding memory plane responsive to a respective read level voltage control signal from the controller.

6. The apparatus of claim 1 , further comprising:
a pass voltage regulator circuit coupled to the global access line decoder circuit of the plurality of global access line decoder circuits and configured to provide the respective pass voltage signals.

7. The apparatus of claim 6 , wherein, during the memory access operation, the controller is further configured to control the pass voltage regulator circuit to provide the respective pass voltage signals having respective voltage profiles associated with a page type.

8. The apparatus of claim 1 , wherein the controller comprises a power control circuit configured to, during the memory access operation, control a global access line decoder circuit to provide a read level voltage signal to a particular one of the plurality of global access lines of the respective global access line bus and to provide the respective pass voltage signals to each remaining global access line of the plurality of global access lines.

9. The apparatus of claim 1 , further comprising a plurality of block controllers, wherein, during the concurrent memory access operations, a block controller of the plurality of block controllers is configured to couple a respective global access line bus to local access lines of a block of a corresponding memory plane selected based on a block selection signal from the controller.

10. The apparatus of claim 9 further comprising a plurality of page buffers, wherein, during the concurrent memory access operations, a page buffer of the plurality of page buffers is configured to latch data from a page of the selected block of the memory plane.

11. The apparatus of claim 1 , wherein the concurrent memory access operations include two or more page types.

12. An apparatus, comprising:
a first memory plane coupled to a first global access line bus;
a second memory plane coupled to a second global access line bus;
a first global access line decoder circuit configured to provide a first read level voltage signal to a respective global access line of the first global access line bus; and
a second global access line decoder circuit configured to provide a second read level voltage signal to a respective global access line of the second global access line bus,
wherein the first global access line decoder circuit comprises a plurality of global access line multiplexer circuits, wherein one of the plurality of global access line multiplexer circuits is configured to provide the first read level voltage signal to the respective global access line of the first global access line bus and remaining global access line multiplexer circuits of the plurality of global access line multiplexer circuits are configured to provide a respective pass voltage signal to remaining global access lines of the plurality of global access lines of the first global access line bus.

13. The apparatus of claim 12 , further comprising:
a first read level voltage regulator circuit configured to provide the first read level voltage signal having a voltage profile based on a first page type of a page of the first memory plane accessed during a memory access operation; and
a second read level voltage regulator circuit configured to provide the second read level voltage signal having a voltage profile based on a second page type of a page of the second memory plane accessed concurrently with the page of the first memory plane during the memory access operation.

14. The apparatus of claim 12 , further comprising at least one pass voltage regulator circuit configured to provide the respective pass voltage signals.

Assignees

• Micron Technology Inc

Inventors

• Rajwade Shantanu R
• Kalavade Pranav
• Tanzawa Toru

Classifications

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title