Method of manufacturing a semiconductor transducer device with multilayer diaphragm and semiconductor transducer device with multilayer diaphragm

Patent metadata

Field	Value
Publication number	US-12191402-B2
Application number	US-201917288847-A
Country	US
Kind code	B2
Filing date	Oct 24, 2019
Priority date	Nov 7, 2018
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

In an embodiment a method includes providing a semiconductor body, forming a sacrificial layer above a surface of the semiconductor body, applying a diaphragm on the sacrificial layer and removing the sacrificial layer by introducing an etchant into openings of the diaphragm, wherein applying the diaphragm comprises applying a first layer, reducing a roughness of a surface of the first layer facing away from the semiconductor body thereby providing a processed surface, and patterning and structuring the first layer to form the openings.

First claim

The invention claimed is:

1. A method for producing a semiconductor transducer device, the method comprising:
providing a semiconductor body;
forming a sacrificial layer above a surface of the semiconductor body;
applying a diaphragm on the sacrificial layer; and
removing the sacrificial layer by introducing an etchant into openings of the diaphragm,
wherein applying the diaphragm comprises:
applying a first layer comprising tungsten, wherein the first layer is a layer of a finished diaphragm with a largest thickness,
reducing a roughness of a surface of the first layer facing away from the semiconductor body thereby providing a processed surface, and
patterning and structuring the first layer to form the openings,

wherein applying the diaphragm comprises applying a third layer comprising at least one of titanium or titanium nitride,
wherein the first layer is applied on a surface of the third layer facing away from the semiconductor body, and
wherein the processed surface has a roughness profile with an arithmetic average between 2 nm and 10 nm inclusive.

2. The method according to claim 1 , wherein reducing the roughness comprises polishing with a chemical-mechanical polishing (CMP).

3. The method according to claim 1 , wherein applying the diaphragm further comprises applying a second layer on the processed surface.

4. The method according to claim 3 , wherein applying the second layer comprises applying titanium and/or titanium nitride.

5. The method according to claim 1 , wherein applying the third layer comprises applying titanium and/or titanium nitride.

6. The method according to claim 1 , further comprising:
applying an electrode layer between the semiconductor body and the sacrificial layer;
forming vias interconnecting the electrode layer and the semiconductor body; and
forming further vias interconnecting the diaphragm and the semiconductor body.

7. The method according to claim 6 , further comprising applying a cover layer between the semiconductor body and the electrode layer.

8. The method according to claim 1 , further comprising applying an etch stop layer between the semiconductor body and the sacrificial layer.

9. The method according to claim 1 , wherein the diaphragm is applied on a substantially flat surface of the sacrificial layer.

10. A method of producing a semiconductor transducer device, the method comprising:
providing a semiconductor body;
forming a sacrificial layer above a surface of the semiconductor body;
applying a diaphragm on the sacrificial layer; and
removing the sacrificial layer by introducing an etchant into openings of the diaphragm,
wherein applying the diaphragm comprises:
applying a third layer comprising at least one of titanium or titanium nitride,
applying a first layer comprising tungsten, wherein the first layer is a layer of a finished diaphragm with a largest thickness, and wherein the first layer is applied on a surface of the third layer facing away from the semiconductor body,
reducing a roughness of a surface of the first layer facing away from the semiconductor body thereby providing a processed surface, wherein the processed surface has a roughness profile with arithmetic average between 2 nm and 10 nm inclusive, and
patterning and structuring the first layer to form the openings.

Assignees

• Sciosense Bv

Inventors

• Faes Alessandro
• Siegert Jörg
• Besling Willem Frederik Adrianus
• Pijnenburg Remco Henricus Wilhelmus

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• B81B2201/0264

  Pressure sensors · CPC title

• B81C1/00158

  Diaphragms, membranes (manufacture process for semi-permeable inorganic membranes B01D67/0039) · CPC title

• H04R31/003

  for diaphragms or their outer suspension · CPC title