Semiconductor device and fabrication method

Patent metadata

Field	Value
Publication number	US-9416004-B2
Application number	US-201514595543-A
Country	US
Kind code	B2
Filing date	Jan 13, 2015
Priority date	Jan 21, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

Semiconductor devices and fabrication methods are provided. In a semiconductor device, a semiconductor substrate includes a first electrode layer having a top surface coplanar with a top surface of the semiconductor substrate. A sacrificial layer is formed on the semiconductor substrate and the first electrode layer. A first mask layer made of a conductive material is formed on the sacrificial layer. The first mask layer and the sacrificial layer are etched until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer. A cleaning process is performed to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings. Conductive plugs are formed in the openings after the cleaning process.

First claim

What is claimed is:

1. A semiconductor fabrication method, comprising:
providing a semiconductor substrate comprising a first electrode layer therein, wherein the first electrode layer has a top surface coplanar with a top surface of the semiconductor substrate;
forming a sacrificial layer on the semiconductor substrate and the first electrode layer;
forming a first mask layer on the sacrificial layer, wherein the first mask layer is made of a conductive material;
etching the first mask layer and the sacrificial layer, by a first etching process, using a patterned layer as an etch mask to etch the first mask layer until a surface of the sacrificial layer is exposed, and a second etching process following the first etching process, using the first mask layer as an etch mask to etch the sacrificial layer, until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer;
performing a cleaning process to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings; and
forming conductive plugs in the openings after the cleaning process.

2. The method according to claim 1 , wherein the first mask layer is made of Ti, TiN, TaN, Al, or a combination thereof.

3. The method according to claim 1 , wherein the first mask layer has a thickness of about 200 Å to about 300 Å.

4. The method according to claim 1 , wherein:
the openings formed in the first mask layer and in the sacrificial layer comprise at least two openings; and
the openings expose surfaces of at least two separate sub-electrodes of the first electrode layer.

5. The method according to claim 1 , further including:
forming a second mask layer on the sacrificial layer before forming the first mask layer, wherein the first mask layer is formed on the second mask layer.

6. The method according to claim 5 , wherein the second mask layer is made of Si 3 N 4 , with a thickness in a range of about 150 Å to about 250 Å.

7. The method according to claim 1 , wherein the first etching process includes:
a pressure of about 5 mTorr to about 15 mTorr;
a power of about 400 W to about 600 W; and
etchant gases of Cl 2 , O 2 , and HBr,
wherein a flow rate of Cl 2 is about 100 sccm to about 150 sccm, a flow rate of O 2 is about 1 to about 5 sccm, and a flow rate of HBr is about 100 to about 150 sccm.

8. The method according to claim 1 , wherein the second etching process includes:
a pressure of about 80 mTorr to about 120 mTorr;
a power of about 200 W to about 400 W; and

etchant gases of Ar and O 2 , wherein a flow rate of Ar is about 30 sccm to about 80sccm, and a flow rate of O 2 is about 200 sccm to about 300 sccm.

9. The method according to claim 1 , wherein:
the conductive plugs are made of Cu, W, Al, or a combination thereof, the conductive plugs being formed by:
forming a conductive film on the surface of the first mask layer and the sidewalls and the bottom surfaces of the openings to fill up the openings; and
using a chemical mechanical polishing process to planarize the conductive film until the surface of the first mask layer is exposed to form the conductive plugs in the openings.

10. A semiconductor fabrication method, comprising:
providing a semiconductor substrate comprising a first electrode layer therein, wherein the first electrode layer has a top surface coplanar with a top surface of the semiconductor substrate;
forming a sacrificial layer on the semiconductor substrate and the first electrode layer;
forming a first mask layer on the sacrificial layer, wherein the first mask layer is made of a conductive material;
etching the first mask layer and the sacrificial layer until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer;
performing a cleaning process to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings,
wherein the cleaning process includes:
a dry cleaning process on the surface of the first mask layer, and the sidewalls and the bottom surfaces of the openings, and
a wet cleaning process on the surface of the first mask layer, and the sidewalls and the bottom surfaces of the openings after the dry cleaning process, and
forming conductive plugs in the openings after the cleaning process.

11. The method according to claim 10 , wherein the dry cleaning process includes:
a pressure of about 90 mTorr to about 100 mTorr;
a power of about 200 W to about 400 W; and
etchant gases of Ar and O 2 ,
wherein a flow rate of Ar is about 250 sccm to about 350 sccm, and a flow rate of O 2 is about 10 sccm to about 30 sccm.

12. The method according to claim 10 , wherein the wet cleaning process includes:
a cleaning agent including diglycolamine and butyrolactone;
a cleaning temperature of about 50° C. to about 100° C.; and
a cleaning time of about 50 minutes to about 80 minutes.

13. The method according to claim 10 , wherein the first mask layer is made of Ti, TiN, TaN, Al, or a combination thereof.

14. The method according to claim 10 , wherein the first mask layer has a thickness of about 200 Å to about 300 Å.

15. The method according to claim 10 , wherein:
the openings formed in the first mask layer and in the sacrificial layer comprise at least two openings; and
the openings expose surfaces of at least two separate sub-electrodes of the first electrode layer.

16. A semiconductor fabrication method, comprising:
providing a semiconductor substrate comprising a first electrode layer therein, wherein the first electrode layer has a top surface coplanar with a top surface of the semiconductor substrate;
forming a sacrificial layer on the semiconductor substrate and the first electrode layer;
forming a first mask layer on the sacrificial layer, wherein the first mask layer is made of a conductive material;
etching the first mask layer and the sacrificial layer until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer;
performing a cleaning process to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings;
forming conductive plugs in the openings after the cleaning process;
forming through-holes in the first mask layer to expose a surface of the sacrificial layer; and
using an isotropic etching process through the through-holes in the first mask layer to remove a portion of the sacrificial layer between the first electrode layer and the first mask layer to form a cavity,
wherein the first mask layer is overhung above the first electrode layer, and the first mask layer is used as a second electrode layer of a pressure sensor.

17. The method according to claim 16 , further including:
forming a second mask layer on the sacrificial layer before forming the first mask layer, wherein the first mask layer is formed on the second mask layer.

18. The method according to claim 17 , wherein the second mask layer is made of Si 3 N 4 , with a thickness in a range of about 150 Å to about 250 Å.

19. The method according to claim 16 , wherein:
the conductive plugs are made of Cu, W, Al, or a combination thereof, the conductive plugs being formed by:
forming a conductive film on the surface of the first mask layer and the sidewalls and the bottom surfaces of the openings to fill up the openings; and
using a chemi

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Fu Guangcai
• Yang Tianlun
• Zhang Xiaoping

Classifications

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P14/61

  using masks · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/4435

  Noble-metal alloys · CPC title

• H10W20/4424

  Copper alloys · CPC title