Method of forming a semiconductor device with capped air-gap spacer

Patent metadata

Field	Value
Publication number	US-12191373-B2
Application number	US-202117526634-A
Country	US
Kind code	B2
Filing date	Nov 15, 2021
Priority date	Sep 30, 2019
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

A method includes: forming a sacrificial gate structure on the active region; forming a spacer structure including a first spacer, a second spacer, and an air-gap spacer, the air-gap spacer capped by bending an upper portion of the second spacer toward an upper portion of the first spacer; forming an insulating structure on the sides of the spacer structure; forming a gap region; and forming a gate structure including a gate dielectric layer, a gate electrode, and a gate capping layer in the gap region. The upper portion of the second spacer is in physical contact with the upper portion of the first spacer on a contact surface, and a lowermost end of the contact surface is on a level higher than an upper surface of the gate electrode with the substrate being a reference base level.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming an active region protruding from a substrate and extending in a first direction;
forming a sacrificial gate structure on the active region and extending a second direction perpendicular to the first direction;
forming a first spacer, a second spacer, and a sacrificial spacer between the first spacer and the second spacer on at least one side of the sacrificial gate structure;
forming a recess region by removing a portion of the active region on the at least one side of the sacrificial gate structure;
forming a source/drain region on the recess region;
forming a first insulating layer on the source/drain region;
forming an air-gap spacer by removing the sacrificial spacer with respect to the first spacer and the second spacer;
forming a liner layer on the first insulating layer and the second spacer so that an upper portion of the second spacer is bent towards an upper portion of the first spacer to cap the air-gap spacer;
removing the liner layer;
forming a second insulating layer on the first insulating layer and the second spacer;
forming a gap region by removing the sacrificial gate structure; and
forming a gate structure by depositing a gate dielectric layer, a gate electrode, and a gate capping layer in the gap region.

2. The method of claim 1 , wherein the upper portion of the second spacer is in physical contact with the upper portion of the first spacer on a contact surface, and
wherein a lowermost end of the contact surface is on a level higher than an upper surface of the gate electrode with the substrate being a reference base level.

3. The method of claim 1 , wherein a width in the first direction of an upper portion of the air-gap spacer is less than a width in the first direction of a lower portion of the air-gap spacer.

4. The method of claim 1 , further comprising forming a third spacer on an external side surface of the second spacer after forming the second spacer, and
wherein an upper portion of the third spacer is bent towards the upper portion of the second spacer.

5. The method of claim 4 , wherein each of the first spacer, the second spacer, and the third spacer is formed of at least one of SiC, SiN, SiO, SiCN, SiOC, and SiOCN.

6. The method of claim 1 , wherein the second insulating layer has a density greater than a density of the first insulating layer.

7. The method of claim 1 , wherein the second insulating layer is a compressive layer formed of silicon oxide with high density oxide to protect from opening of an upper portion of the air-gap spacer.

8. The method of claim 1 , further comprising performing a planarization process before forming the gap region, and
wherein an upper surface of the first spacer, an upper surface of the second spacer, and an upper surface of the gate capping layer are substantially coplanar with each other.

9. The method of claim 1 , wherein the second insulating layer is in contact with an upper surface of the first spacer and an upper surface of the sacrificial gate structure.

10. The method of claim 1 , wherein in forming the air-gap spacer, a lower portion of the sacrificial spacer is remained as a lower sacrificial spacer.

11. The method of claim 1 , wherein the second insulating layer has a first portion in parallel to an upper surface of the substrate and an extended second portion bent from the first portion to cover an upper surface of the second spacer.

12. A method of manufacturing a semiconductor device, the method comprising:
forming a sacrificial gate structure on a substrate;
forming a spacer structure on sides of the sacrificial gate structure; and
forming an insulating structure on sides of the spacer structure,
wherein forming the spacer structure comprises:
forming first spacers on the sides of the sacrificial gate structure;
forming sacrificial spacers on external sides of the first spacers;
forming second spacers on external sides of the sacrificial spacers; and
forming air-gap spacers by removing the sacrificial spacers with respect to the first spacers and the second spacers,

wherein forming the insulating structure comprises:
forming a first insulating layer on the sides of the spacer structure after forming the second spacers;
forming a liner layer on the first insulating layer after forming the air-gap spacers so that an upper portion of each of the second spacers is bent towards an upper portion of each of the first spacers;
removing the liner layer; and
forming a second insulating layer on the first insulating layer.

13. The method of claim 12 , wherein the liner layer is formed to extend onto an upper surface of the sacrificial gate structure while the air-gap spacer is capped by the second spacer and the liner layer.

14. The method of claim 12 ,
wherein the second insulating layer horizontally overlaps the upper portion of the second spacers, and
wherein an oxygen content in the second insulating layer is greater than an oxygen content in the first insulating layer.

15. The method of claim 12 , wherein the liner layer has a first portion in parallel to an upper surface of the substrate and an extended second portion bent from the first portion to cover an upper surface of the second spacers.

16. The method of claim 12 , further comprising:
forming recess regions in the substrate on both sides of the sacrificial gate structure before forming the insulating structure;
forming source/drain regions on the recess regions;
forming a gap region by removing sacrificial gate structure; and
forming a gate structure by depositing a gate dielectric layer, a gate electrode, and a gate capping layer in the gap region.

17. The method of claim 16 , wherein the upper portion of the second spacer is in physical contact with the upper portion of the first spacer on a contact surface, and
wherein a lowermost end of the contact surface is on a level higher than an upper surface of the gate electrode with the substrate being a reference base level.

18. The method of claim 16 , wherein an upper surface of the gate capping layer, upper surfaces of the first spacers, and upper surfaces of the second spacers are substantially coplanar with each other.

19. A method of manufacturing a semiconductor device, the method comprising:
forming an active region on a substrate;
forming a sacrificial gate structure on the active region;
forming a spacer structure including a first spacer, a second spacer, and an air-gap spacer between the first spacer and the second spacer;
forming source/drain regions on the active region and on both sides of the sacrificial gate structure;
forming an insulating structure on the sides of the spacer structure and the source/drain regions;
forming a liner layer on the insulating structure and the second spacer so that the upper portion of the second spacer is bent toward the upper portion of the first spacer to cap the air gap spacer;
removing the liner layer;
forming a gap region by removing the sacrificial gate structure; and
forming a gate structure by depositing a gate dielectric layer, a gate electrode, and a gate capping layer in the gap region,
wherein the upper portion of the second spacer is in physical contact with the upper portion of the first spacer on a contact surface,
wherein a lowermost end of the contact surface is on a level higher than an upper surface of the gate electrode with the substrate being a reference base level, and
wherein an uppermost end of the air-ga

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Sangkoo
• Kim Sungsoo
• Min Sunki
• Kim Iksoo
• Roh Donghyun

Classifications

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10D30/795

  being in lateral device isolation regions, e.g. STI · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D64/021 Primary

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title