High performance interconnect

Patent metadata

Field	Value
Publication number	US-12189550-B2
Application number	US-202318347236-A
Country	US
Kind code	B2
Filing date	Jul 5, 2023
Priority date	Oct 22, 2012
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

First claim

What is claimed is:

1. An apparatus comprising:
a port to couple to another device over an interconnect, and the port comprises:
protocol circuitry to:
generate a flit based on a cache-coherent interconnect protocol, wherein the flit comprises a plurality of slots to carry a plurality of messages in the flit, and a slot in the plurality of slots is to carry at least a portion of a request message, the request message comprises: an opcode field, a source identifier field, and a destination identifier field; and
send the flit to the other device over the interconnect, wherein routing of the flit is based on at least one of the source identifier field or the destination identifier field.

2. The apparatus of claim 1 , wherein the flit further comprises a cyclic redundancy check (CRC) field to include a CRC value determined for the flit.

3. The apparatus of claim 1 , wherein the plurality of flits comprise at least three slots, and each slot in the at least three slots is configured to carry a respective one of the plurality of messages.

4. The apparatus of claim 1 , wherein a second slot in the plurality of slots is to carry a different second message.

5. The apparatus of claim 4 , wherein the second slot comprises a respective opcode field, a respective source identifier field, and a respective destination identifier field.

6. The apparatus of claim 1 , wherein the opcode field is to carry an opcode corresponding to a type of the request message, the source identifier field is to include a source identifier corresponding to a source of the request message, and the destination identifier field is to include a destination identifier corresponding to a destination for the request message.

7. The apparatus of claim 1 , wherein the port is to receive a second flit over the interconnect from the other device, the second flit comprises a plurality of slots, and one of the plurality of slots of the second flit comprises a response to the request message.

8. The apparatus of claim 1 , wherein the flit comprises a type field to indicate whether the flit comprises protocol data or link layer control data, wherein the flit comprises a type field value to indicate that the flit comprises protocol data, and the request message comprises protocol data.

9. The apparatus of claim 8 , wherein the port is to send a second flit with link layer control data, and the type field of the second flit indicates that the second flit comprises a link layer control flit.

10. The apparatus of claim 9 , wherein one or more of a plurality of slots are defined to be reserved in link layer control flits.

11. The apparatus of claim 1 , wherein the interconnect comprises a plurality of physical lanes.

12. A method comprising:
identifying a request to send from a first device to a second device on a link, wherein the link and the request are based on a cache-coherent interconnect protocol;
generating a first flit, wherein the first flit is based on a flit format defined by the cache-coherent protocol, the flit format comprises a plurality of slots to respectively carry a plurality of messages, and a particular slot in the plurality of slots of the first flit carries the request, wherein the request comprises a destination identifier field to identify a destination of the request and a source identifier field to identify a source of the request; and
sending the first flit from the first device to the second device on the link, wherein the first flit is routed to the second device based on at least one of the destination identifier field or the source identifier field.

13. The method of claim 12 , wherein the plurality of slots of the first flit further comprise a second slot to carry a different second message.

14. The method of claim 13 , wherein the different second message comprises a response to a different request.

15. The method of claim 12 , further comprising:
receiving, at the first device, a second flit on the link, wherein the second flit is based on the flit format;
identifying a response to the request in one of the plurality of slots of the second flit, wherein the response comprises a corresponding destination identifier field and a corresponding source identifier field; and
processing the response at the first device.

16. A system comprising:
a first device;
a second device coupled to the first device by an interconnect, wherein the second device comprises a port to interface with the interconnect, and the port comprises circuitry to:
generate a flit based on a cache-coherent interconnect protocol, wherein the flit comprises a plurality of slots to carry a plurality of messages in the flit, a slot in the plurality of slots is to carry at least a portion of a request message, and the request message comprises: an opcode field, a source identifier field, and a destination identifier field; and
send the flit to the other device over the interconnect, wherein routing of the flit is based on at least one of the source identifier field or the destination identifier field.

17. The system of claim 16 , wherein the second device comprises a processor device.

18. The system of claim 17 , wherein the first device comprises an accelerator device.

19. The system of claim 17 , wherein the first device comprises a memory device.

20. The system of claim 16 , wherein the flit further comprises:
a type field to indicate whether the flit comprises a protocol flit or a link layer control flit; and
a CRC field a cyclic redundancy check (CRC) field to include a CRC value determined for the flit.

Assignees

• Intel Corp

Inventors

• Safranek Robert J
• Blankenship Robert G
• Iyer Venkatraman
• Willey Jeff
• Beers Robert
• Jue Darren S
• Kumar Arvind A
• Das Sharma Debendra
• Swanson Jeffrey C
• Fahim Bahaa
• Geetha Vedaraman
• Spink Aaron T
• Spagna Fulvio
• Shah Rahul R
• Iyer Sitaraman V
• Nale William Harry
• Das Abhishek
• Johnson Simon P
• Dhillon Yuvraj S
• Liu Yen-Cheng
• Ramanujan Raj K
• Maddox Robert A
• Hum Herbert H
• Gupta Ashish

Classifications

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• H04L9/0662

  with particular pseudorandom sequence generator · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F13/4068

  Electrical coupling · CPC title