High performance interconnect physical layer

Patent metadata

Field	Value
Publication number	US-10216674-B2
Application number	US-201615393366-A
Country	US
Kind code	B2
Filing date	Dec 29, 2016
Priority date	Oct 22, 2012
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.

First claim

What is claimed is:

1. An apparatus comprising:
physical layer logic, link layer logic, and protocol layer logic, wherein the physical layer logic is to:
generate a supersequence comprising a sequence comprising an electrical ordered set (EOS) and a plurality of training sequences, the plurality of training sequences comprises a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.

2. The apparatus of claim 1 , wherein the training sequence payloads are scrambled with a pseudorandom bit sequence (PRBS).

3. The apparatus of claim 2 , wherein the PRBS comprises PRBS23.

4. The apparatus of claim 2 , wherein the physical layer logic comprises a linear feedback shift register (LFSR) to generate the PRBS.

5. The apparatus of claim 4 , wherein the LFSR comprises a 23-bit Fibonacci LFSR.

6. The apparatus of claim 5 , wherein the LFSR implements a generator polynomial comprising: x 23 +x 21 +x 16 +x 8 +x 5 +x 2 + 1.

7. The apparatus of claim 1 , wherein the EOS comprises an electrical idle exit ordered set (EIEOS).

8. The apparatus of claim 7 , wherein:
the EIEOS comprises a 16 byte ordered set,
bytes 0, 2, 4, 6, 8, 10, 12, and 14 of the EIEOS comprise a value 8′h00, and
bytes 1, 3, 5, 7, 9, 11, 13, and 15 of the EIEOS comprise a value 8′hFF.

9. The apparatus of claim 1 , wherein the plurality of training states comprise a detect state, a polling state, a configuration state, and a loopback state.

10. The apparatus of claim 9 , wherein the supersequence comprises a detect supersequence corresponding to the detect state and the predefined number of training sequences in the detect supersequence comprise a series of six training sequences.

11. The apparatus of claim 9 , wherein the supersequence comprises a polling supersequence corresponding to the polling state and the predefined number of training sequences in the polling supersequence comprise a series of thirty training sequences.

12. The apparatus of claim 11 , wherein a loopback supersequence corresponding to the loopback state also has a series of thirty training sequences, the training sequences in the polling supersequence have a first value and the training sequences in the loopback supersequence have a second value.

13. The apparatus of claim 1 , wherein the physical layer logic comprises a transmitter to send the supersequence on each of a plurality of lanes of a link.

14. The apparatus of claim 13 , wherein the supersequence is sent to another device and the physical layer logic comprises a receiver to receive an instance of the supersequence from the other device.

15. A processor device comprising:
a processor node; and
physical layer logic to receive a supersequence comprising an electrical idle exit ordered set (EIEOS) and a series of training sequences, wherein the series of training sequences comprises a predefined number of training sequences corresponding to a particular one of a plurality of states in a state machine, each training sequence in the series of training sequences comprises a respective header and payload, the payloads of the series of training sequences are to be scrambled by a pseudorandom bit sequence (PRBS) and the headers of the plurality of training sequences are to be unscrambled; and
determine the particular state from the supersequence.

16. The processor device of claim 15 , further comprising a controller comprising the physical layer logic, wherein the controller further comprises link layer logic and protocol layer logic.

17. The processor device of claim 15 , further comprising a linear feedback shift register (LFSR) to generate the PRBS.

18. The processor device of claim 17 , wherein the LFSR comprises a 23-bit Fibonacci LFSR.

19. The processor device of claim 15 , wherein the training sequence headers comprise a type field to indicate a particular one of the plurality of states.

20. The processor device of claim 19 , wherein the training sequence headers further comprise a lane numbering field.

21. An apparatus comprising:
a controller corresponding to a first processor to interface between at least the first processor to recognize a first instruction set and a second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising protocol layer logic, link layer logic, and physical layer logic, the physical layer logic to:
generate a supersequence comprising a sequence comprising an electrical ordered set (EOS) and a plurality of training sequences, wherein the plurality of training sequences comprises a predefined number of training sequences corresponding to a particular one of a plurality of training states in a state machine, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be scrambled and the training sequence headers of the plurality of training sequences are to be unscrambled,
wherein the plurality of training states comprise a detect state, a polling state, a configuration state, and a loopback state.

22. A system comprising:
a first processor;
a second processor connected to the first processor by an interconnect, the second processor comprising protocol layer logic, link layer logic, and physical layer logic, the physical layer logic to send a supersequence to the first processor over the interconnect, wherein the supersequence comprises an electrical ordered set (EOS) and a series of training sequences, the series of training sequences comprises a predefined number of training sequences corresponding to a particular one of a plurality of link training states in a state machine, each training sequence in the series of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the series of training sequences are to be scrambled and the training sequence headers of the series of training sequences are to be unscrambled,
wherein the first processor comprises physical layer logic to:
receive the supersequence; and
determine the particular state from the supersequence.

23. The system of claim 22 , wherein the first processor comprises protocol layer logic, link layer logic, and physical layer logic, the physical layer logic to receive the supersequence from the second processor and generate instances of the supersequence to send to the second processor.

24. The system of claim 22 , wherein the EOS comprises an electrical idle exit ordered set (EIEOS).

Assignees

• Intel Corp

Inventors

• Iyer Venkatraman
• Jue Darren S
• Iyer Sitaraman V

Classifications

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4004 Primary

  Coupling between buses · CPC title

• G06N20/00

  Machine learning · CPC title

• Y02D10/151

  Cross-Sectional Technologies · mapped topic

• G06N99/005

  Physics · mapped topic