Three-dimensional memory devices with reduced cell interference and fabrication methods thereof

Patent metadata

Field	Value
Publication number	US-12185536-B2
Application number	US-202117336208-A
Country	US
Kind code	B2
Filing date	Jun 1, 2021
Priority date	Feb 17, 2020
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

Embodiments of a three-dimensional (3D) memory device and method for forming the 3D memory device are provided. In an example, the 3D memory device includes a plurality of conductor layers extending over a substrate, a channel structure vertically extending through the conductor layers to the substrate, and a source structure extending through the conductor layers to the substrate. The channel structure may include a blocking layer having a plurality of blocking portions disconnected from one another. Each of the blocking portions may include (i) a vertical blocking portion under a respective conductor layer, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective conductor layer. The channel structure may also include a memory layer having a plurality of memory portions disconnected from one another, each of the memory portions under and in contact with the respective vertical blocking portion.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a plurality of conductor layers;
a channel structure vertically extending through the plurality of conductor layers, the channel structure comprising:
a blocking layer comprising a plurality of blocking portions disconnected from one another, wherein each of the plurality of blocking portions comprises (i) a vertical blocking portion under a respective one of the plurality of conductor layers, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective one of the plurality of conductor layers; and
a memory layer comprising a plurality of memory portions disconnected from one another, each of the plurality of memory portions being arranged adjacent to and in direct contact with the respective vertical blocking portion, and a top surface of a blocking portion of the plurality of blocking portions that covers a lateral surface of a corresponding conductor layer of the plurality of conductor layers remaining coplanar with a top surface of a corresponding memory portion of the plurality of memory portions;

a high-k dielectric layer and an adhesive layer between each of the plurality of blocking portions and the respective one of the plurality of conductor layers; and
a source structure comprising a doped region and a source contact that comprises a conductive material and extending through the plurality of conductor layers, the conductive material of the source contact being in direct contact with the doped region.

2. The 3D memory device of claim 1 , wherein the blocking layer comprises silicon oxynitride, and the memory layer comprises silicon nitride.

3. The 3D memory device of claim 1 , further comprises a sealing structure in which the plurality of conductor layers, the channel structure, and the source structure are located, wherein the sealing structure is in contact with a tunneling layer of the channel structure and encloses the plurality of conductor layers, the blocking layer, and the memory layer.

4. The 3D memory device of claim 3 , wherein the sealing structure comprises an air gap between adjacent lateral blocking portions.

5. The 3D memory device of claim 3 , wherein the sealing structure comprises silicon oxide.

6. The 3D memory device of claim 1 , wherein the high-k dielectric layer comprises (i) a vertical high-k portion between the respective one of the plurality of conductor layers and the respective vertical blocking portion, and (ii) at least one lateral high-k portion between the respective one of the plurality of conductor layers and the respective lateral blocking portion.

7. The 3D memory device of claim 1 , further comprising:
a sealing structure in contact with a tunneling layer of the channel structure and extending laterally to cover the source contact of the source structure.

8. The 3D memory device of claim 1 further comprising:
a sealing structure in contact with a tunneling layer of the channel structure and comprising an insulating spacer between the source contact of the source structure and the plurality of conductor layers.

9. The 3D memory device of claim 8 , wherein:
the insulating spacer is in contact with sidewalls of the high-k dielectric layer and the adhesive layer.

10. The 3D memory device of claim 1 , wherein the adhesive layer comprises (i) a vertical adhesive portion between the respective one of the plurality of conductor layers and the respective vertical blocking portion, and (ii) at least one lateral adhesive portion between the respective one of the plurality of conductor layers and the respective lateral blocking portion.

11. The 3D memory device of claim 1 , wherein:
the channel structure comprises a tunneling layer; and
the 3D memory device further comprises a sealing structure arranged between the tunneling layer and the source contact of the source structure.

12. The 3D memory device of claim 1 , wherein:
a thickness of the blocking layer is in a range of about 40 Å to about 100 Å.

13. The 3D memory device of claim 1 , wherein:
the blocking layer comprises a dielectric metal oxide having a dielectric constant greater than 7.9.

14. The 3D memory device of claim 1 , wherein:
the adhesive layer is arranged between the high-k dielectric layer and the respective one of the plurality of conductor layers.

15. The 3D memory device of claim 1 , further comprises a sealing structure in direct contact with a tunneling layer of the channel structure and enclosing the plurality of conductor layers, the blocking layer, and the memory layer, wherein the sealing structure extends from the channel structure to be in direct contact with the conductive material of the source contact.

16. A three-dimensional (3D) memory device, comprising:
a plurality of conductor layers;
a channel structure vertically extending through the plurality of conductor layers and comprising:
a blocking layer comprising a plurality of blocking portions disconnected from one another, wherein each of the plurality of blocking portions comprises (i) a vertical blocking portion under a respective one of the plurality of conductor layers, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective one of the plurality of conductor layers; and
a memory layer comprising a plurality of memory portions disconnected from one another, each of the plurality of memory portions being arranged adjacent to and in direct contact with the respective vertical blocking portion, and a top surface of a blocking portion of the plurality of blocking portions that covers a lateral surface of a corresponding conductor layer of the plurality of conductor layers remaining coplanar with a top surface of a corresponding memory portion of the plurality of memory portions;

a source structure comprising a source contact and extending through the plurality of conductor layers, the source contact comprising a conductive material; and
a sealing structure in contact with a tunneling layer of the channel structure and laterally extending to cover the conductive material of the source contact.

17. The 3D memory device of claim 16 , further comprising:
a high-k dielectric layer and an adhesive layer between each of the plurality of blocking portions and the respective one of the plurality of conductor layers.

18. The 3D memory device of claim 17 , wherein:
sidewalls of the high-k dielectric layer and the adhesive layer are in contact with the sealing structure.

19. The 3D memory device of claim 17 , wherein:
the adhesive layer comprises (i) a vertical adhesive portion between the respective one of the plurality of conductor layers and the respective vertical blocking portion, and (ii) at least one lateral adhesive portion between the respective one of the plurality of conductor layers and the respective lateral blocking portion.

20. The 3D memory device of claim 16 , wherein:
the source structure comprises a doped region, the source contact being in direct contact with the doped region.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xue Lei
• Yao Lan
• Shiue Chia-Chann
• Liu Xiaoxin

Classifications

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/30 Primary

  characterised by the memory core region · CPC title