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Vertical memory devices with quantum-dot charge storage cells
US8969947B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969947-B2 |
| Application number | US-201113042051-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 7, 2011 |
| Priority date | Apr 27, 2010 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory device comprising: a substrate; a semiconductor column longitudinally extending from the substrate in a first direction perpendicular to the substrate; a plurality of interlayer insulating layers disposed on a sidewall of the semiconductor column and spaced apart along the first direction and having surfaces oriented perpendicular to the semiconductor column; a plurality of charge storage cells disposed on the sidewall of the semiconductor col…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8969947B2 cover?
- A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plu…
- Who is the assignee on this patent?
- Lee Jae-Goo, Choi Jung-Dal, Park Young-Woo, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10D64/035. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).